公开(公告)号：US06830027B1

公开(公告)日：2004-12-14

申请号：US10866603

申请日：2004-06-10

申请人： Makoto Segawa ,  Haruhiko Yamada ,  Masato Amano ,  Yuichi Tamura

发明人： Makoto Segawa ,  Haruhiko Yamada ,  Masato Amano ,  Yuichi Tamura

IPC分类号： F02B7700

CPC分类号： F02D41/0087 ,  F02D41/123 ,  F02D41/1443 ,  F02D41/1456 ,  F02D41/1495

摘要： A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the cylinders is operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. Operating parameters of a vehicle driven by the engine is detected. The all-cylinder operation or the partial-cylinder operation is performed according to the detected operating parameters. An oxygen concentration sensor is provided in an exhaust system corresponding to the at least one cylinder which is halted during the partial-cylinder operation. A failure of the oxygen concentration sensor is diagnosed in a predetermined operating condition including a fuel-cut operation of the engine upon deceleration. The partial-cylinder operation is permitted after completion of the failure diagnosis.

摘要翻译： 一种用于具有多个气缸的内燃机的控制系统和用于在其中操作所有气缸的全气缸操作之间进行切换的切换机构和其中至少一个气缸的部分气缸操作 停止了 检测由发动机驱动的车辆的操作参数。 根据检测到的操作参数进行全气缸操作或部分气缸操作。 在与部分气缸操作期间停止的至少一个气缸相对应的排气系统中设置氧浓度传感器。 氧浓度传感器的故障在包括减速时的发动机的燃料切断动作的预定动作条件下被诊断。 完成故障诊断后允许部分气缸操作。

公开(公告)号：US5751035A

公开(公告)日：1998-05-12

申请号：US718657

申请日：1996-09-23

申请人： Yasushi Kameda ,  Makoto Segawa

发明人： Yasushi Kameda ,  Makoto Segawa

IPC分类号： H01L21/822 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  H01L29/78 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： A semiconductor device is provided with at least one transistor formed on a semiconductor substrate, the transistor being provided with a conductive sidewall spacer, and at least one conductive film formed so as to face a gate of the transistor via an insulative film, the conductive film covering at least an entire region of a gate region of the transistor and acting as a capacitor electrode. The conductive sidewall spacer and the conductive film are connected together. A potential is supplied to the conductive sidewall spacer and the conductive film, the potential being different from a potential of the gate of the transistor.

摘要翻译： 半导体器件设置有形成在半导体衬底上的至少一个晶体管，所述晶体管设置有导电侧壁间隔物，以及至少一个导电膜，其通过绝缘膜形成为面对晶体管的栅极，所述导电膜 覆盖晶体管的栅极区域的至少整个区域并充当电容器电极。 导电侧壁间隔物和导电膜连接在一起。 向导电侧壁间隔物和导电膜提供电位，该电位与晶体管的栅极的电位不同。

公开(公告)号：US5467317A

公开(公告)日：1995-11-14

申请号：US328049

申请日：1994-10-24

申请人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

发明人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C11/34

CPC分类号： G11C8/14

摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

摘要翻译： 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

公开(公告)号：US5459423A

公开(公告)日：1995-10-17

申请号：US77737

申请日：1993-06-18

申请人： Yasumitsu Nozawa ,  Shigeto Mizukami ,  Makoto Segawa

发明人： Yasumitsu Nozawa ,  Shigeto Mizukami ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G05F1/46 ,  G11C7/22 ,  G11C11/407 ,  G11C11/413 ,  H01L27/10 ,  H03K5/13 ,  H04B1/40 ,  H03K5/153 ,  H03K5/159

CPC分类号： G11C7/22 ,  G05F1/466 ,  H03K5/133

摘要： A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit generates a second supply voltage (constant voltage) on the basis of the first supply voltage, and supplies the constant voltage to this delay circuit, so that a stable constant delay time can be obtained by the delay circuit without being subjected to the influence of fluctuations of the first supply voltage. All the circuit elements are formed on the same semiconductor substrate. Further, it is preferable to construct the constant voltage supply circuit in such a way that the output voltage thereof is programmable.

摘要翻译： 延迟电路插在由第一电源电压驱动的第一和第二电路系统之间。 延迟电路延迟由第一电路系统施加的信号，然后将延迟的信号发送到第二电路系统。 特别地，恒压电源电路基于第一电源电压产生第二电源电压（恒定电压），并将恒定电压提供给该延迟电路，从而可以通过延迟电路获得稳定的恒定延迟时间 而不受第一电源电压波动的影响。 所有电路元件形成在相同的半导体衬底上。 此外，优选构造恒定电压供给电路，使得其输出电压是可编程的。

公开(公告)号：US4939691A

公开(公告)日：1990-07-03

申请号：US260427

申请日：1988-10-20

申请人： Shigeto Mizukami ,  Makoto Segawa

发明人： Shigeto Mizukami ,  Makoto Segawa

IPC分类号： G11C11/417 ,  G11C11/409 ,  G11C11/419

CPC分类号： G11C11/419

摘要： In a static random access memory, when data is written into said plurality of memory cells, a write enable signal is set at a low level, and after the data write is completed, the write enable signal is set at a high level. In response to a level change of the write enable signal from a low level to a high level, a pulse generator generates a pulse signal in "1" level and with a given pulse width. In response to this pulse signal, a first MOS transistor is turned on to short paired bit lines. This pulse signal turns on second and third MOS transistors. Then, the potentials on the paired bit lines are pulled up to a power source potential. As a result, of the two bit lines, the bit line which has been set at a low potential immediately after data is written, is charged. A pulse extension/inverting circuit extends the pulse width of the pulse signal generated by a pulse generator by a given time period, and inverts a logical state of the pulse signal. During a period that the first MOS transistor shorts the bit lines to place the equal potentials on the bit lines, the pulse signal .phi.WRD output from the pulse extension/inverting circuit is kept in "0" level. During this period, therefore, the output data of two AND gates is "0" level irrespective of the sensed data from a read circuit and the supply of the sensed data from the read circuit to a data output circuit is stopped.

摘要翻译： 在静态随机存取存储器中，当将数据写入所述多个存储单元时，写入使能信号被设置为低电平，并且在数据写入完成之后，写使能信号被设置为高电平。 响应于写使能信号从低电平到高电平的电平变化，脉冲发生器产生具有“1”电平和给定脉冲宽度的脉冲信号。 响应于该脉冲信号，第一MOS晶体管导通短对成对的位线。 该脉冲信号接通第二和第三MOS晶体管。 然后，成对位线上的电位被拉到电源电位。 结果，在两个位线之间，在写入数据之后立即被设置为低电位的位线被充电。 脉冲扩展/反相电路将由脉冲发生器产生的脉冲信号的脉冲宽度延长给定的时间周期，并且使脉冲信号的逻辑状态反相。 在第一MOS晶体管使位线短路以将相等电位置于位线的期间内，从脉冲扩展/反相电路输出的脉冲信号phi WRD保持为“0”电平。 因此，在此期间，与读取电路的感测数据无关，两个与门的输出数据为“0”电平，并且停止从读取电路向数据输出电路的感测数据的供给。

公开(公告)号：US07438665B2

公开(公告)日：2008-10-21

申请号：US11589474

申请日：2006-10-30

申请人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

发明人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

IPC分类号： B60W10/04

CPC分类号： F02D41/0087 ,  B60W2510/1005 ,  B60W2520/10 ,  F01L13/0005 ,  F01L2800/00 ,  F02D41/0225 ,  F02D2200/023 ,  F02D2200/024 ,  F02D2200/0404 ,  F02D2200/0406 ,  F02D2200/0414 ,  F02D2200/703 ,  F16H63/50 ,  Y10T477/675 ,  Y10T477/679 ,  Y10T477/68

摘要： A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

摘要翻译： 一种用于具有多个气缸的内燃机的控制系统和用于在其中操作所有多个气缸的全气缸操作之间进行切换的切换机构和其中多个气缸中的至少一个 气瓶停止。 基于由发动机驱动的车辆的检测到的操作参数来确定用于执行部分缸操作的条件。 当从执行部分气缸操作的状态的车辆操作状态起的预定时间段内检测到的操作参数满足预定的连续状态时，修改确定的结果，使得可以继续部分气缸操作 已经改变为不满足执行部分气缸操作的条件的另一个车辆操作状态。

公开(公告)号：US20070042863A1

公开(公告)日：2007-02-22

申请号：US11589474

申请日：2006-10-30

申请人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

发明人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

IPC分类号： B60W10/04

CPC分类号： F02D41/0087 ,  B60W2510/1005 ,  B60W2520/10 ,  F01L13/0005 ,  F01L2800/00 ,  F02D41/0225 ,  F02D2200/023 ,  F02D2200/024 ,  F02D2200/0404 ,  F02D2200/0406 ,  F02D2200/0414 ,  F02D2200/703 ,  F16H63/50 ,  Y10T477/675 ,  Y10T477/679 ,  Y10T477/68

摘要： A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

摘要翻译： 一种用于具有多个气缸的内燃机的控制系统和用于在其中操作所有多个气缸的全气缸操作之间进行切换的切换机构和其中多个气缸中的至少一个 气瓶停止。 基于由发动机驱动的车辆的检测到的操作参数来确定用于执行部分缸操作的条件。 当从执行部分气缸操作的状态的车辆操作状态起的预定时间段内检测到的操作参数满足预定的连续状态时，修改确定的结果，使得可以继续部分气缸操作 已经改变为不满足执行部分气缸操作的条件的另一个车辆操作状态。

公开(公告)号：US06388938B2

公开(公告)日：2002-05-14

申请号：US09812362

申请日：2001-03-20

申请人： Takao Nakajima ,  Makoto Segawa

发明人： Takao Nakajima ,  Makoto Segawa

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1006 ,  G11C7/1051

摘要： There is provided a semiconductor memory device capable of preventing the deterioration of access characteristics between output signal lines. The semiconductor memory device comprises: first and second cell arrays, each of which has the same number of memory cells; first through (2n−1)-th (n≧1) output selection control circuits; first through (2n−1)-th output transistor circuits which are provided so as to correspond to the first through (2n−1)-th output selection control circuits, and each of which receives the output of a corresponding one of the output transistor circuits; and first through (4n−2)-th output signal lines, each of the first and second cell arrays being divided into k (k≧2) first through k-th section parts, each of which has 2n−1 first through (2n−1)-th output parts and at least one auxiliary input/output part, the i-th (i=1, . . . , n−1) output selection control part receiving the output of the (2i−1)-th input/output part of each of the first through k-th section parts of the first cell array via the (2i−1)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the first cell array via the 2i-th output signal line, the n-th output selection control part receiving the output of the (2n−1)-th input/output part of each of the first through k-th section parts of the first cell array via the (2n−1)-th output signal line and receiving the output of the auxiliary input/output part of each of the section parts of the first cell array via the 2n-th output signal line, and the (n+i)-th (i=1, . . . , n−1) output control circuit receiving the output of the (2i−1)-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i−1)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i)-th output signal line.

公开(公告)号：US6037638A

公开(公告)日：2000-03-14

申请号：US34316

申请日：1998-03-04

申请人： Mitsuhiro Abe ,  Yoichi Suzuki ,  Makoto Segawa

发明人： Mitsuhiro Abe ,  Yoichi Suzuki ,  Makoto Segawa

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： The gates 31, 32, 33 and 34 of a pair of driver transistors Q1, Q2 and a pair of address-selecting transistors Q3, Q4 are arranged so as to be perpendicular to bit lines BL, /BL. The drain regions of the driver transistors Q1, Q2 forming a flip-flop are arranged point-symmetrically around an element isolating region. The source regions of the driver transistors Q1, Q2 are arranged point-symmetrically. Similarly, the address-selecting transistors Q3, Q4 are arranged point-symmetrically. An upper wiring layer connected to two gates of the transistors are arranged so as to be perpendicular to the bit lines BL, /BL. Two Vss lines are formed in the same layer as that for the bit lines BL, /BL and arranged on both sides of the bit lines BL, /BL in parallel thereto. The Vss lines are connected to the source regions of the driver transistors. With this construction, the bi-stability of a memory cell used for a semiconductor memory device, such as a SRAM, is improved, so that the low-voltage operation and the hold characteristic are improved and software errors are removed. In addition, the aspect ratio of the cell is changed from the aspect ratio of a conventional, longitudinally extending cell to the aspect ratio of a laterally extending cell, so that the lengths of the bit lines are decreased to achieve a high speed operation.

摘要翻译： 一对驱动晶体管Q1，Q2和一对地址选择晶体管Q3，Q4的栅极31,32,33和34被布置成垂直于位线BL / BL。 形成触发器的驱动晶体管Q1，Q2的漏极区域围绕元件隔离区域对称布置。 驱动晶体管Q1，Q2的源极区域对称布置。 类似地，地址选择晶体管Q3，Q4被点对称地排列。 连接到晶体管的两个栅极的上部布线层被布置成垂直于位线BL / BL。 两条Vss线形成在与位线BL，/ BL相同的层中，并且平行布置在位线BL，/ BL两侧。 Vss线连接到驱动晶体管的源极区域。 利用这种结构，用于诸如SRAM的半导体存储器件的存储单元的双稳态性得到改善，从而提高了低电压操作和保持特性，并且消除了软件错误。 此外，单元的纵横比从常规的纵向延伸单元的纵横比变化到横向延伸单元的纵横比，从而减小位线的长度以实现高速操作。

公开(公告)号：US5440512A

公开(公告)日：1995-08-08

申请号：US44115

申请日：1993-04-08

申请人： Takayuki Harima ,  Makoto Segawa

发明人： Takayuki Harima ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C7/10 ,  G11C11/409 ,  G11C11/413 ,  G11C11/417

CPC分类号： G11C7/1051 ,  G11C7/1057

摘要： A semiconductor memory device includes an address input circuit for receiving an address signal and outputting an internal address signal corresponding to the received address signal; an address decoder for decoding the internal address signal and outputting a decoded signal; a memory cell array having a plurality of memory cells each capable of storing data, as selected by the decoded signal, the selected memory cell outputting memory cell data; and an output circuit for outputting a truth data and false data at the same time in accordance with the output memory cell data of the selected memory cell.

摘要翻译： 半导体存储器件包括地址输入电路，用于接收地址信号并输出​​对应于接收到的地址信号的内部地址信号; 地址解码器，用于解码内部地址信号并输出​​解码信号; 具有多个存储单元的存储单元阵列，每个存储单元都能够存储由所述解码信号选择的输出存储单元数据的所选存储单元的数据; 以及输出电路，用于根据所选存储单元的输出存储单元数据同时输出真值数据和伪数据。