公开(公告)号：US20210295907A1

公开(公告)日：2021-09-23

申请号：US17024410

申请日：2020-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063

Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.

公开(公告)号：US20210257023A1

公开(公告)日：2021-08-19

申请号：US17199243

申请日：2021-03-11

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  ANH LY ,  THUAN VU ,  STANLEY HONG ,  FENG ZHOU ,  XIAN LIU ,  NHAN DO

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C7/06

Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

公开(公告)号：US20210232893A1

公开(公告)日：2021-07-29

申请号：US17233006

申请日：2021-04-16

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： FARNOOD MERRIKH BAYAT ,  XINJIE GUO ,  DMITRI STRUKOV ,  NHAN DO ,  HIEU VAN TRAN ,  VIPIN TIWARI ,  MARK REITEN

IPC: G06N3/04 ,  G06N3/063 ,  G06F3/06

Abstract: Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a converter for converting a target weight into a target current and a comparator for comparing the target current to an output current from the selected non-volatile memory cell during a verify operation. In another embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a digital-to-analog converter for converting a target weight comprising digital bits into a target voltage, a current-to-voltage converter for converting an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator for comparing the output voltage to the target voltage during a verify operation.

公开(公告)号：US20200349421A1

公开(公告)日：2020-11-05

申请号：US16449201

申请日：2019-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEPHEN TRINH ,  THUAN VU ,  STANLEY HONG ,  VIPIN TIWARI ,  MARK REITEN ,  NHAN DO

IPC: G06N3/063 ,  G11C16/04 ,  G11C11/54 ,  G06F17/16

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.

公开(公告)号：US20190080767A1

公开(公告)日：2019-03-14

申请号：US16025039

申请日：2018-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： VIPIN TIWARI ,  NHAN DO

IPC: G11C16/10 ,  G11C16/28

Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.

公开(公告)号：US20170125429A1

公开(公告)日：2017-05-04

申请号：US15295022

申请日：2016-10-17

Applicant: Silicon Storage Technology, Inc.

Inventor： CHIEN-SHENG SU ,  FENG ZHOU ,  JENG-WEI YANG ,  HIEU VAN TRAN ,  NHAN DO

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.