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公开(公告)号：US20050229054A1
公开(公告)日：2005-10-13
申请号：US11086655
申请日：2005-03-23
CPC分类号： G11C29/50012 , G01R31/3016 , G11C29/02
摘要： An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.
摘要翻译： 可以在正常运行状态和测试运行状态下运行的集成半导体存储器包括具有用于施加输入信号的输入端的电流脉冲电路。 电流脉冲电路经由用于承载电流的互连件连接到输出端子。 在测试操作状态下，当前脉冲电路在第一测试周期中产生具有第一预定持续时间的至少一个第一电流脉冲，以及在随后的第二测试周期中具有第二未知持续时间的至少一个第二电流脉冲。 除了在正常操作状态下在互连上流动的第一电流之外，第二电流在第一测试周期期间在互连上流动，并且第三电流在测试操作状态期间在第二测试周期期间流动。
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公开(公告)号：US20050225917A1
公开(公告)日：2005-10-13
申请号：US11100617
申请日：2005-04-07
IPC分类号： G11C29/12 , H01L21/66 , H01L23/58 , H01L27/108 , H02H9/04
CPC分类号： G11C29/12005 , G11C29/12
摘要： Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.
摘要翻译： 集成半导体电路，特别是动态随机存取存储器包括用于从外部施加的电源电压产生内部电压电平的多个发生器电路。 在测试期间，内部电压电平由发生器电路输出端产生的输出电压改变为外部施加的测试电压。 如果测试电压超出公差范围，则半导体电路可能被破坏。 与发生器电路并联连接的保护电路限制输出电压。
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公开(公告)号：US20050052238A1
公开(公告)日：2005-03-10
申请号：US10934396
申请日：2004-09-07
申请人： Joerg Vollrath , Marcin Gnat , Ullrich Menczigar
发明人： Joerg Vollrath , Marcin Gnat , Ullrich Menczigar
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45672 , H03F3/45708 , H03F2203/45508
摘要： A differential amplifier circuit has two input transistors, a load element, and a current source. A terminal for an input voltage is connected to a control terminal of a first input transistor. A terminal for a reference voltage is connected to a control terminal of a second input transistor. The two input transistors are connected in parallel between the load element and a terminal of the current source. A terminal for an internal reference potential is connected to a further terminal of the current source. A regulating circuit, is connected to the terminal for the voltage and to the terminal for the reference potential, and regulates the potential of the circuit dependent on changes in the reference voltage. Fluctuations of the reference voltage are compensated by regulation of the internal reference potential. As a result, the operating point of the circuit is stabilized independently of fluctuations of the reference voltage.
摘要翻译： 差分放大器电路具有两个输入晶体管，负载元件和电流源。 用于输入电压的端子连接到第一输入晶体管的控制端子。 用于参考电压的端子连接到第二输入晶体管的控制端子。 两个输入晶体管并联在负载元件和电流源的端子之间。 用于内部参考电位的端子连接到电流源的另一个端子。 调节电路连接到端子的电压和端子作为参考电位，并根据参考电压的变化调节电路的电位。 参考电压的波动通过内部参考电位的调节来补偿。 结果，独立于参考电压的波动，电路的工作点是稳定的。
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公开(公告)号：US06564346B1
公开(公告)日：2003-05-13
申请号：US09455855
申请日：1999-12-07
申请人： Joerg Vollrath , Ulf Lederer , Peter Oswald , Thomas Hladschik , Zschunke Andreas , Rausch Harold
发明人： Joerg Vollrath , Ulf Lederer , Peter Oswald , Thomas Hladschik , Zschunke Andreas , Rausch Harold
IPC分类号： G11C2900
CPC分类号： G11C29/72 , G01R31/31935 , G11C29/56
摘要： A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed devices and transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device. Failure classification is provided by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type.
摘要翻译： 根据本发明的用于提供压缩比特失败映射的方法包括以下步骤：测试半导体器件以确定故障设备并传送故障信息以显示压缩位图，通过指定位图上的相应故障位置的区域 半导体器件。 通过在位图的指定区域中指定失效区域的形状和尺寸来提供故障分类，使得故障区域形状和尺寸表示故障类型。
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公开(公告)号：US06453433B1
公开(公告)日：2002-09-17
申请号：US09281021
申请日：1999-03-30
申请人： Joerg Vollrath
发明人： Joerg Vollrath
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C11/401 , G11C29/02 , G11C29/50 , G11C2029/5004
摘要： Disclosed is a method and apparatus for testing a semiconductor memory having a plurality of memory cells arranged in rows and columns and a plurality of sense amplifiers, each for amplifying memory cell signals of a common row or column. In an illustrative embodiment of the method, a voltage level or test pattern is written into at least one target cell of the memory cells. A word line coupled to the target cell is then activated and subsequently deactivated, to thereby modify the voltage level stored in the cell, while the associated sense amplifier is prevented from refreshing the cell as the word line is activated, e.g., by disabling the sense amplifier. A test bit line voltage is then applied to a bit line coupled to the cell to charge the same. Data is then read from the target cell with settings of the associated sense amplifier enabled, and compared to the original voltage level written into the cell. The process is repeated for different test bit line voltages. The method can be used to determine the signals at the sense amplifiers during normal operation of the memory, without employing complex and costly picoprobes.
摘要翻译： 公开了一种用于测试半导体存储器的方法和装置，该半导体存储器具有排列成行和列的多个存储单元和多个读出放大器，每个用于放大公共行或列的存储单元信号。 在该方法的说明性实施例中，将电压电平或测试图案写入存储器单元的至少一个目标单元。 然后，耦合到目标单元的字线被激活并且随后被去激活，从而修改存储在单元中的电压电平，同时当字线被激活时防止相关的读出放大器刷新单元，例如通过禁用该感测 放大器 然后将测试位线电压施加到耦合到该单元的位线以对其进行充电。 然后从相关读出放大器的设置使能的目标单元读取数据，并将其与写入单元的原始电压电平进行比较。 针对不同的测试位线电压重复该过程。 该方法可用于在存储器的正常操作期间确定读出放大器处的信号，而不需要使用复杂和昂贵的皮秒。
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公开(公告)号：US07719868B2
公开(公告)日：2010-05-18
申请号：US11715839
申请日：2007-03-08
申请人： Joerg Vollrath
发明人： Joerg Vollrath
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/18 , G11C11/4097 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： An integrated semiconductor memory has memory cells, with at least one pair of bit lines which comprises a first bit line and a second bit line, and with at least one sense amplifier which has the first bit line and the second bit line connected to it. The bit lines respectively have a first conductor track structure and a second conductor track structure, where the memory cells are respectively connected to the second conductor track structure, and where the first conductor track structure is respectively interposed between the sense amplifier and the second conductor track structure of the respective bit line and is arranged at a greater distance from the substrate area than the respective second conductor track structure.
摘要翻译： 集成半导体存储器具有存储单元，其中至少一对位线包括第一位线和第二位线，以及至少一个读出放大器，其具有与其连接的第一位线和第二位线。 位线分别具有第一导体轨道结构和第二导体轨道结构，其中存储单元分别连接到第二导体轨道结构，并且其中第一导体轨道结构分别插入在读出放大器和第二导体轨道之间 相对于位线的结构，并且布置在距离基板区域比相应的第二导体轨道结构更远的距离处。
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公开(公告)号：US20100039845A1
公开(公告)日：2010-02-18
申请号：US12193267
申请日：2008-08-18
申请人： Joerg Vollrath , Marcin Gnat
发明人： Joerg Vollrath , Marcin Gnat
CPC分类号： G11C7/18 , G11C5/063 , G11C7/02 , G11C11/4097 , H01L27/0207 , H01L27/10885
摘要： An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.
摘要翻译： 集成电路包括包括多个存储单元的存储单元阵列。 第一多个位线位于第一平面中。 第一组多个位线电耦合到第一组存储器单元。 第二多个位线位于与第一平面不同的第二平面中。 第二组多个位线电耦合到第二组存储器单元。
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38.发明授权Integrated semiconductor circuit comprising a transistor and a strip conductor 有权集成半导体电路，包括晶体管和带状导体公开(公告)号：US07372095B2
公开(公告)日：2008-05-13
申请号：US11213342
申请日：2005-08-26
申请人： Joerg Vollrath
发明人： Joerg Vollrath
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833
摘要： An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor (11) extends along a first direction (x) in the area of the transistor. The second source/drain region (2) is arranged offset with respect to the first source/drain region (1) in the first direction (x). The transistor thus formed has an inversion channel (K1) that only extends between two corner areas (1a, 2a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.
摘要翻译： 集成半导体电路包括晶体管和带状导体（11）。 晶体管包括第一（1）和第二源/漏区（2）和栅电极。 带状导体（11）至少通过栅极电介质与半导体本体电绝缘，并在晶体管的区域中形成栅电极。 带状导体（11）沿着晶体管的区域中的第一方向（x）延伸。 第二源极/漏极区域（2）在第一方向（x）上相对于第一源极/漏极区域（1）偏移地布置。 这样形成的晶体管具有仅在第一和第二源极/漏极区域彼此面对的两个拐角区域（1a，2a）之间延伸的反转沟道（K 1），即比在 常规晶体管。
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公开(公告)号：US07224627B2
公开(公告)日：2007-05-29
申请号：US11100617
申请日：2005-04-07
IPC分类号： G11C7/00
CPC分类号： G11C29/12005 , G11C29/12
摘要： Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.
摘要翻译： 集成半导体电路，特别是动态随机存取存储器包括用于从外部施加的电源电压产生内部电压电平的多个发生器电路。 在测试期间，内部电压电平由发生器电路输出端产生的输出电压改变为外部施加的测试电压。 如果测试电压超出公差范围，则半导体电路可能被破坏。 与发生器电路并联连接的保护电路限制输出电压。
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公开(公告)号：US20050289413A1
公开(公告)日：2005-12-29
申请号：US11145192
申请日：2005-06-06
CPC分类号： G11C29/1201 , G11C29/14 , G11C29/38
摘要： An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit that generates the third data record on the output side from the data records fed to the combination circuit on the input side to ascertain based on the third data record whether the first and second data records have been fed to the combination circuit on the input side. The combination circuit generates the datum of the third data record with the first data value, if the first and second data records were fed to the combination circuit on the input side.
摘要翻译： 集成半导体存储器包括存储第一数据记录的存储器单元具有至少一个具有第一或第二数据值的数据，而第二数据记录具有至少一个具有第一或第二数据值的数据。 集成半导体存储器具有组合电路，其从在输入侧馈送到组合电路的数据记录在输出侧产生第三数据记录，以基于第三数据记录来确定第一和第二数据记录是否被馈送到 输入侧的组合电路。 如果第一和第二数据记录被馈送到输入侧的组合电路，则组合电路产生具有第一数据值的第三数据记录的数据。
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