公开(公告)号：US06365937B1

公开(公告)日：2002-04-02

申请号：US09310538

申请日：1999-05-12

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L2362

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device for integrated circuit is formed in a substrate and contains pad contact, rail contact and a deep oxide in a trench in the substrate which isolates pad and rail contacts. The substrate is doped with a first dopant type with a first concentration. A second dopant type in a first inner and a first outer region forms the pad contact; both regions are formed on the substrate. The first inner region is doped higher than the first outer region. Similarly a second dopant type in a second inner and a second outer region forms the rail contact; both regions are formed on the substrate. The second inner region is doped higher than the second outer region. Buried layers are formed of the first dopant type in a second concentration under the pad and rail contacts and under the deep oxide.

摘要翻译： 用于集成电路的静电放电保护装置形成在衬底中，并且在衬底中的沟槽中包含衬垫接触，轨道接触和深氧化物，隔离衬垫和轨道触点。 衬底掺杂有第一浓度的第一掺杂剂类型。 在第一内部和第一外部区域中的第二掺杂剂形式形成焊盘触点; 两个区域形成在基板上。 第一内部区域被掺杂高于第一外部区域。 类似地，在第二内部和第二外部区域中的第二掺杂剂形式形成轨道接触; 两个区域形成在基板上。 第二内部区域被掺杂高于第二外部区域。 掩埋层在第二浓度下由第一掺杂剂形成在焊盘和轨道触点下方以及深氧化物下方。

公开(公告)号：US06297998B1

公开(公告)日：2001-10-02

申请号：US09678979

申请日：2000-10-05

申请人： Scott D. Van de Graaff ,  Stephen R. Porter

发明人： Scott D. Van de Graaff ,  Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C7/1045 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： A method and apparatus for testing of semiconductor memory devices. In one embodiment, a test mode of operation is defined for a memory device. In a normal mode of operation, a row line than addressed memory cell is asserted in response to applied external signals corresponding to the beginning of a write-back phase of a read-modify-write cycle. The row line is deasserted on response to applied external signals corresponding to the end of the write-back phase. In the test mode of operation, the row line is asserted in response to the appropriate applied external signals, but deassertion in response to the appropriate applied external signals is suppressed. Instead, deassertion of the row line is forced only upon expiration of a programmable, predetermined time interval following initiation of the write-back phase. The programmable delay can be established by means of an R-C time constant delay circuit. Programmability may be achieved in various ways, including through the provision of metal options selected during the fabrication process, or, alternatively through the provision of laser-actuable fuses or voltage-actuable antifuses. The programmable forced write-back time facilitates reliable comparative testing of multiple parts, and compensates for part-to-part process variations which potentially impact operational performance of different parts to different degrees.

摘要翻译： 一种用于半导体存储器件测试的方法和装置。 在一个实施例中，为存储器件定义了测试操作模式。 在正常操作模式中，响应于对应于读 - 修改 - 写周期的回写阶段的开始的外部信号，断言比寻址存储单元的行行。 响应于对应于回写阶段结束的外部信号，行行被取消置位。 在测试操作模式下，响应于适当的外部信号，行线被断言，但是抑制了对适当的外部信号的响应。 相反，只有在启动回写阶段之后的可编程的预定时间间隔期满时才迫使行线的取消取消。 可以通过R-C时间常数延迟电路建立可编程延迟。 可编程性可以通过各种方式实现，包括通过提供在制造过程期间选择的金属选项，或者通过提供激光可激活的熔丝或电压可启动的反熔丝。 可编程强制回写时间有助于对多个零件进行可靠的比较测试，并补偿部件到零件的过程变化，这些变化会对不同零件的运行性能产生不同程度的影响。

公开(公告)号：US5903502A

公开(公告)日：1999-05-11

申请号：US977757

申请日：1997-11-25

申请人： Stephen R. Porter

发明人： Stephen R. Porter

IPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/026 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50 ,  G11C7/12 ,  G11C11/401 ,  G11C2029/5004

摘要： A method and circuit for rapidly equilibrating paired digit lines of a memory array of a dynamic random access memory device is described. The equilibrate circuit includes a bias-circuit coupled to sense amplifier circuitry for adjusting the equilibrate voltage during testing. A method is described for testing memory cell margin by adjusting the equilibrate voltage until an error is detected. The bias circuit is described as a pull-up transistor coupled to a common mode of a cross-coupled n-sense amplifier.

公开(公告)号：US07466618B2

公开(公告)日：2008-12-16

申请号：US10930517

申请日：2004-08-31

申请人： Stephen R. Porter ,  Scott J. Derner

发明人： Stephen R. Porter ,  Scott J. Derner

IPC分类号： G11C17/18

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

摘要翻译： 提供了通过轻掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得该区域的电阻以非线性方式响应电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。

公开(公告)号：US07033867B2

公开(公告)日：2006-04-25

申请号：US10793309

申请日：2004-03-04

申请人： Stephen R. Porter

发明人： Stephen R. Porter

IPC分类号： H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region. In one illustrative embodiment, the method comprises forming a trench in a semiconducting substrate, forming at least one layer of insulating material in the trench, forming a conductive member in the trench above the at least one layer of insulating material, forming at least one doped active region in the substrate adjacent the trench, forming at least one conductive contact that is coupled to the conductive member and forming at least one conductive contact that is coupled to the at least one doped active region.

摘要翻译： 反熔丝装置包括定位在沟槽中的绝缘层，位于绝缘层之上的导电构件，导电构件的至少一部分位于沟槽内，导电构件适于具有施加到其上的至少一个编程电压，以及 至少一个形成在衬底中的与沟槽相邻的掺杂有源区。 反熔丝还包括耦合到导电构件的至少一个导电触点，以及耦合到掺杂有源区的至少一个导电触点。 在一个说明性实施例中，该方法包括在半导体衬底中形成沟槽，在沟槽中形成至少一层绝缘材料，在至少一层绝缘材料之上的沟槽中形成导电构件，形成至少一个掺杂 形成至少一个与所述导电部件耦合的导电接触，并且形成至少一个耦合到所述至少一个掺杂有源区的导电接触。

公开(公告)号：US07020039B2

公开(公告)日：2006-03-28

申请号：US10998483

申请日：2004-11-29

申请人： Luan C. Tran ,  Stephen R. Porter ,  Scot M. Graham ,  Steven E. Howell

发明人： Luan C. Tran ,  Stephen R. Porter ,  Scot M. Graham ,  Steven E. Howell

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/816 ,  G11C2207/002 ,  G11C2207/005 ,  Y10S257/906

摘要： A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。

公开(公告)号：US06992939B2

公开(公告)日：2006-01-31

申请号：US10764675

申请日：2004-01-26

申请人： Stephen R. Porter

发明人： Stephen R. Porter

IPC分类号： G11C7/00

CPC分类号： G11C29/025 ,  G11C11/401 ,  G11C29/02

摘要： The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of programming a first memory cell associated with a first digit line to a first data value, programming a second memory cell associated with a second digit line to a second data value, the second data value being complementary with respect to the first data value, firing a first sense amplifier associated with the first digit line, firing a second sense amplifier associated with the second digit line after a time delay with respect to the act of firing the first sense amplifier associated with the first digit line, detecting a measured data value associated with the second digit line, and comparing the measured data value to the second data value to determine whether the first digit line is short circuited to the second digit line. The apparatus may comprise a first sense amplifier that is associated with a first digit line, a second sense amplifier that is associated with a second digit line, and a circuit that delays a firing operation of the second sense amplifier with respect to a firing operation of the first sense amplifier to allow detection of a short circuit between the first digit line and the second digit line.

摘要翻译： 所公开的实施例涉及用于识别集成电路装置中的短路的方法和装置。 该方法可以包括将与第一数字线相关联的第一存储器单元编程为第一数据值的动作，将与第二数字线相关联的第二存储器单元编程为第二数据值，第二数据值相对于 第一数据值，触发与第一数字线相关联的第一读出放大器，在相对于触发与第一数字线相关联的第一读出放大器的动作的时间延迟之后点火与第二数字线相关联的第二读出放大器， 检测与第二数字线相关联的测量数据值，以及将测量的数据值与第二数据值进行比较，以确定第一数字线是否短路到第二数字线。 该装置可以包括与第一数字线相关联的第一读出放大器，与第二数字线相关联的第二读出放大器，以及延迟相对于第二数字线的点火操作的第二读出放大器的点火操作的电路 第一读出放大器允许检测第一数字线和第二数字线之间的短路。

公开(公告)号：US06859408B2

公开(公告)日：2005-02-22

申请号：US10230637

申请日：2002-08-29

申请人： Stephen R. Porter ,  Scott J. Derner

发明人： Stephen R. Porter ,  Scott J. Derner

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C11/00 ,  G11C17/18 ,  H01L21/82 ,  H01L23/525

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method and apparatus for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

摘要翻译： 用于通过轻掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得该区域的电阻以非线性方式响应于电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。

公开(公告)号：US06723618B2

公开(公告)日：2004-04-20

申请号：US10206602

申请日：2002-07-26

申请人： Russell Meyer ,  Jeffrey W. Honeycutt ,  Stephen R. Porter

发明人： Russell Meyer ,  Jeffrey W. Honeycutt ,  Stephen R. Porter

IPC分类号： H01L218238

CPC分类号： H01L21/76205

摘要： Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench. Additional implementations are contemplated.

摘要翻译： 描述了现场隔离结构和形成场隔离结构的方法。 在一个实施方案中，该方法包括蚀刻单晶硅衬底内的沟槽。 沟槽具有侧壁和基底，底部包括单晶硅。 介电材料形成在沟槽的侧壁上。 外延单晶硅从沟槽的底部至少部分介电材料生长。 在外延单晶硅上形成绝缘层。 根据一个实施方案，本发明包括在包含单晶硅的衬底内形成的场隔离结构。 场隔离结构包括具有侧壁的沟槽。 电介质材料被容纳在沟槽内的侧壁上。 单晶硅被接纳在侧壁的电介质材料之间的沟槽内。 绝缘层被接纳在沟槽内的单晶硅上。 考虑附加实现。

公开(公告)号：US06515925B2

公开(公告)日：2003-02-04

申请号：US09805933

申请日：2001-03-15

申请人： Scot M. Graham ,  Scott J. Derner ,  Stephen R. Porter

发明人： Scot M. Graham ,  Scott J. Derner ,  Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.