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    SEMICONDUCTOR DEVICE
    31.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20100001349A1

    公开(公告)日：2010-01-07

    申请号：US12495501

    申请日：2009-06-30

    申请人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

    发明人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823425 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/66825

    摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

    摘要翻译： 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

    MANUFACTURING METHOD FOR SEMICONDUCTOR DEBICE
    33.
    发明申请
    MANUFACTURING METHOD FOR SEMICONDUCTOR DEBICE 有权
    半导体器件的制造方法

    公开(公告)号：US20120299154A1

    公开(公告)日：2012-11-29

    申请号：US13459740

    申请日：2012-04-30

    申请人： Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

    发明人： Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

    IPC分类号： H01L29/00 ,  H01L21/336 ,  H01L21/04

    CPC分类号： H01L29/6659 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

    摘要： A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

    摘要翻译： 通过在基板上形成第一绝缘层，在第一绝缘层上进行第一次氮化，形成第二绝缘层，依次进行第一和第二退火，制造具有改善的负偏压温度不稳定寿命特性的半导体器件 第二绝缘层以形成第三绝缘层，其中所述第二退火在比所述第一退火更高的温度和不同的气体下进行。 在第三绝缘层上进行第二次氮化，以形成第四绝缘层，并且在第四绝缘层上顺序的第三和第四退火形成第五绝缘层。 第三退火在比第一退火更高的温度下进行，第四退火在比第二退火更高的温度下进行，并且具有比第三退火不同的气体。

    Method of manufacturing semiconductor device using stress memorization technique
    35.
    发明授权
    Method of manufacturing semiconductor device using stress memorization technique 有权
    使用应力记忆技术制造半导体器件的方法

    公开(公告)号：US08772095B2

    公开(公告)日：2014-07-08

    申请号：US13495062

    申请日：2012-06-13

    申请人： Seok-Hoon Kim ,  Sang-Su Kim ,  Chung-Geun Koh ,  Sun-Ghil Lee ,  Jin-Yeong Joe

    发明人： Seok-Hoon Kim ,  Sang-Su Kim ,  Chung-Geun Koh ,  Sun-Ghil Lee ,  Jin-Yeong Joe

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

    摘要： The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

    摘要翻译： 制造半导体器件包括提供支撑栅电极的衬底，通过执行预非晶化注入（PAI）工艺并且将C或N注入到源/漏区中来对位于栅电极的两侧的源/漏区进行非晶化和掺杂， 漏极区域或与PAI工艺分离，在衬底上形成应力诱导层以覆盖非晶化源极/漏极区域，并且随后通过对衬底退火来使源极/漏极区域再结晶。 然后可以去除应力诱导层。 此外，在区域已经非晶化之后，或仅仅在非晶化源极/漏极区域的上部，C或N可以被注入到整个源极/漏极区域中。

    Method of forming oxide layer, and method of manufacturing semiconductor device
    37.
    发明申请
    Method of forming oxide layer, and method of manufacturing semiconductor device 审中-公开
    形成氧化物层的方法和制造半导体器件的方法

    公开(公告)号：US20100055856A1

    公开(公告)日：2010-03-04

    申请号：US12461896

    申请日：2009-08-27

    申请人： Soo-Jin Hong ,  Jong-Ryeol Yoo ,  Dong-Woon Shin ,  Si-Young Choi ,  Sun-Ghil Lee

    发明人： Soo-Jin Hong ,  Jong-Ryeol Yoo ,  Dong-Woon Shin ,  Si-Young Choi ,  Sun-Ghil Lee

    IPC分类号： H01L21/8242 ,  H01L21/31

    CPC分类号： H01L21/02236 ,  H01L21/022 ,  H01L21/31155 ,  H01L21/31641 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897

    摘要： A method of forming an oxide layer on a trench, a method of forming a semiconductor device, and a semiconductor device, the method of forming an oxide layer on a trench including forming a first trench in a first portion of a substrate and a second trench in a second portion of the substrate, the first portion being different from the second portion, performing a plasma doping process on at least one of the first portion and the second portion to implant an impurity therein, and performing an oxidation process to form an oxide layer on the substrate, a thickness of the oxide layer being determined by the impurity implanted in the substrate.

    摘要翻译： 在沟槽上形成氧化物层的方法，形成半导体器件的方法和半导体器件，在沟槽上形成氧化物层的方法，包括在衬底的第一部分中形成第一沟槽和第二沟槽 在所述衬底的第二部分中，所述第一部分与所述第二部分不同，在所述第一部分和所述第二部分中的至少一个上执行等离子体掺杂工艺以在其中注入杂质，并进行氧化处理以形成氧化物 层，该氧化物层的厚度由注入衬底中的杂质决定。