公开(公告)号：US20100001349A1

公开(公告)日：2010-01-07

申请号：US12495501

申请日：2009-06-30

申请人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

发明人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC分类号： H01L27/088

CPC分类号： H01L21/823425 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/66825

摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

摘要翻译： 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US08716093B2

公开(公告)日：2014-05-06

申请号：US13428900

申请日：2012-03-23

申请人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

发明人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823425 ,  H01L21/28273 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

摘要翻译： 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US20120184079A1

公开(公告)日：2012-07-19

申请号：US13428900

申请日：2012-03-23

申请人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

发明人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/28273 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

摘要翻译： 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US08877583B2

公开(公告)日：2014-11-04

申请号：US13728622

申请日：2012-12-27

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/285 ,  H01L21/768 ,  H01L49/02

CPC分类号： H01L21/285 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76889 ,  H01L27/10855 ,  H01L28/91

摘要： In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.

摘要翻译： 在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层 在比第一温度高的第二温度下进行处理。 因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。 因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。

公开(公告)号：US09368495B2

公开(公告)日：2016-06-14

申请号：US14576368

申请日：2014-12-19

申请人： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

发明人： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC分类号： H01L21/00 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

摘要： A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

摘要翻译： 半导体器件分别在衬底上包括衬底，第一有源鳍片和第二有源鳍片，分别在第一有源鳍片和第二有源鳍片上的多个第一外延层，多个第二外延层， 多个第一外延层，将多个第二外延层彼此连接的桥接层以及桥接层上的第三外延层。

公开(公告)号：US09972716B2

公开(公告)日：2018-05-15

申请号：US14826439

申请日：2015-08-14

申请人： Jin-Bum Kim ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Su-Jin Jung ,  Bon-Young Koo

发明人： Jin-Bum Kim ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Su-Jin Jung ,  Bon-Young Koo

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/32 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/3221 ,  H01L29/165 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/785

摘要： Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

公开(公告)号：US08470703B2

公开(公告)日：2013-06-25

申请号：US13105195

申请日：2011-05-11

申请人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

发明人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

摘要翻译： 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

公开(公告)号：US20110306205A1

公开(公告)日：2011-12-15

申请号：US13105195

申请日：2011-05-11

申请人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

发明人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

摘要翻译： 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

公开(公告)号：US20080116487A1

公开(公告)日：2008-05-22

申请号：US11782237

申请日：2007-07-24

申请人： Byeong-Chan Lee ,  Si-Young Choi ,  Young-Pil Kim ,  Yong-Hoon Son ,  In-Soo Jung ,  Jin-Bum Kim

发明人： Byeong-Chan Lee ,  Si-Young Choi ,  Young-Pil Kim ,  Yong-Hoon Son ,  In-Soo Jung ,  Jin-Bum Kim

IPC分类号： H01L29/739 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/2683 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/1083

摘要： Transistors having a high carrier mobility and devices incorporating the same are fabricated by forming a preliminary semiconductor layer in a semiconductor substrate at both sides of a gate pattern. A source/ drain semiconductor layer having a heterojunction with the semiconductor substrate is formed by irradiating a laser beam onto the preliminary semiconductor layer. The source/drain semiconductor layer is formed in a recrystallized single crystal structure.

摘要翻译： 具有高载流子迁移率的晶体管和其结合的器件通过在栅极图案的两侧在半导体衬底中形成初步半导体层来制造。 通过将激光束照射到初步半导体层上，形成与半导体衬底具有异质结的源/漏半导体层。 源/漏半导体层以再结晶单晶结构形成。

公开(公告)号：US08586223B2

公开(公告)日：2013-11-19

申请号：US12862625

申请日：2010-08-24

申请人： Hyo-Rim Bak ,  Jin-Bum Kim ,  Wan-Mook Lim ,  Hae-Kwon Yoon ,  Myoung-Han Ryu

发明人： Hyo-Rim Bak ,  Jin-Bum Kim ,  Wan-Mook Lim ,  Hae-Kwon Yoon ,  Myoung-Han Ryu

IPC分类号： H01M6/10 ,  H01M2/02

CPC分类号： H01M10/4235 ,  H01M2/023 ,  H01M10/651 ,  H01M10/654

摘要： A secondary battery that includes a cylindrical can, an electrode assembly arranged in a jelly-role configuration within the cylindrical can and having a core extending about an axis thereof and a hollow center pin arranged within the core of the electrode assembly and having an inner diameter and an outer diameter, the outer diameter forming ones of a pair of radial lengths diametrically opposite from each other, each of said pair of radial lengths extending from the outer diameter of the center pin to an external surface of the core, wherein the sum of the pair of radial lengths is in the range of 5% to 54% of the inner diameter of the center pin.

摘要翻译： 一种二次电池，其包括圆筒形罐，电极组件，其布置在圆筒形罐内的果冻状结构中，并且具有围绕其轴线延伸的芯和布置在电极组件的芯部内的中空中心销，并且具有内径 外直径形成一对径向长度彼此直径相对的外径，所述一对径向长度从中心销的外径延伸到芯的外表面，其中， 一对径向长度在中心销的内径的5％至54％的范围内。