公开(公告)号：US09230851B2

公开(公告)日：2016-01-05

申请号：US14175488

申请日：2014-02-07

Applicant: Texas Instruments Incorporated

Inventor： Simon John Molloy ,  Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Hong Yang ,  Seetharaman Sridhar ,  Hideaki Kawahara

IPC: H01L21/336 ,  H01L21/763 ,  H01L29/66

CPC classification number: H01L21/763 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/7397 ,  H01L29/7811

Abstract: A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a trench dielectric liner and filled by a first polysilicon layer. The surface of the trench dielectric liner is etched, wherein dips in the trench dielectric liner are formed relative to a top surface of the first polysilicon layer which results in forming a protrusion including the first polysilicon layer. The first polysilicon layer is etched to remove at least a portion of the protrusion. A second dielectric layer is formed over at least the trench after etching the first polysilicon layer. A second polysilicon layer is deposited. The second polysilicon layer is etched to remove it over the trench and provide a patterned second polysilicon layer on the top side of the semiconductor layer.

Abstract translation: 制造半导体器件的方法包括从半导体层的顶侧形成至少一个沟槽，其中沟槽衬有沟槽电介质衬垫并由第一多晶硅层填充。 蚀刻沟槽电介质衬垫的表面，其中沟槽电介质衬里中的凹陷相对于第一多晶硅层的顶表面形成，导致形成包括第一多晶硅层的突起。 蚀刻第一多晶硅层以去除突起的至少一部分。 在蚀刻第一多晶硅层之后，至少在沟槽上形成第二电介质层。 沉积第二多晶硅层。 蚀刻第二多晶硅层以将其去除在沟槽上并且在半导体层的顶侧上提供图案化的第二多晶硅层。

公开(公告)号：US09136381B1

公开(公告)日：2015-09-15

申请号：US14546274

申请日：2014-11-18

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Hideaki Kawahara

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/482

CPC classification number: H01L29/7832 ,  H01L23/4824 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/783 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/0001

Abstract: Semiconductor device includes MOSFET having planar cells on an epitaxial semiconductor surface of a first type providing a drain drift region. A first and second epitaxial column formed in the semiconductor surface are doped a second type. A split gate includes planar gates between the epitaxial columns including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second type in the drift region abuts the epitaxial columns. A source of the first type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

Abstract translation: 半导体器件包括在提供漏极漂移区的第一类型的外延半导体表面上具有平面单元的MOSFET。 形成在半导体表面中的第一和第二外延柱掺杂第二类型。 分离栅极包括在包括MOS栅极（MOS栅极）和二极管栅极（二极管栅极）的外延柱之间的平面栅极。 漂移区域中第二类型的体区邻接外延柱。 身体区域中的第一类型的源包括靠近MOS栅极的第一源极部分和靠近二极管栅极的第二源极部分。 垂直漂移区域使用身体区域下方的漂移区域来提供排水。 连接器将二极管栅极短路到第二源极部分以提供集成通道二极管。 MOS栅极与第一源极部分电气隔离。

公开(公告)号：US11444191B2

公开(公告)日：2022-09-13

申请号：US16990284

申请日：2020-08-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

公开(公告)号：US20200373424A1

公开(公告)日：2020-11-26

申请号：US16990284

申请日：2020-08-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

公开(公告)号：US10741684B2

公开(公告)日：2020-08-11

申请号：US15283523

申请日：2016-10-03

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

公开(公告)号：US20190259868A1

公开(公告)日：2019-08-22

申请号：US16277719

申请日：2019-02-15

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Seetharaman Sridhar ,  Satoshi Suzuki ,  Simon John Molloy

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

公开(公告)号：US10256337B2

公开(公告)日：2019-04-09

申请号：US15427489

申请日：2017-02-08

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Seetharaman Sridhar ,  Simon John Molloy ,  Satoshi Suzuki

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

公开(公告)号：US10153220B2

公开(公告)日：2018-12-11

申请号：US15785778

申请日：2017-10-17

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L23/057 ,  H01L23/08 ,  H01L25/16 ,  H01L25/04 ,  H01L21/48 ,  H01L25/00 ,  H01L21/78 ,  H01L23/13

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

公开(公告)号：US10121716B2

公开(公告)日：2018-11-06

申请号：US15634232

申请日：2017-06-27

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Tom Grebs ,  Simon John Molloy

IPC: H01L21/52 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/00 ,  H01L23/373

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

公开(公告)号：US10109614B2

公开(公告)日：2018-10-23

申请号：US15053089

申请日：2016-02-25

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/065 ,  H01L23/06 ,  H01L25/18 ,  H01L25/00 ,  H01L23/053 ,  H01L23/00 ,  H01L21/50 ,  H01L23/13 ,  H01L23/14 ,  H01L29/06 ,  H01L23/498

Abstract: An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.