公开(公告)号：US10903306B2

公开(公告)日：2021-01-26

申请号：US16163606

申请日：2018-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Hideaki Kawahara ,  Sameer P. Pendharkar

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/762 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08

Abstract: Embodiments of a deep trench capacitor are disclosed. In one example a plurality of deep trenches is located in a first region of a semiconductor wafer, the first region having a first conductivity type. A corresponding dielectric layer is located on a surface of each of the plurality of deep trenches, and a corresponding doped polysilicon filler is located within each of the dielectric layers. Dielectric-filled trenches are located between each of the dielectric layers and the surface of the semiconductor wafer.

公开(公告)号：US09653342B2

公开(公告)日：2017-05-16

申请号：US14548029

申请日：2014-11-19

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Hong Yang ,  Christopher Boguslaw Kocon ,  Yufei Xiong ,  Yunlong Liu

IPC: H01L21/762 ,  H01L21/28 ,  H01L21/765 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/765 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/945

Abstract: A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

公开(公告)号：US20160240667A1

公开(公告)日：2016-08-18

申请号：US15138955

申请日：2016-04-26

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Malloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

Abstract translation: 半导体器件包括中等电压MOSFET，其在包含场耦合到MOSFET的源电极的场板的RESURF沟槽之间具有垂直漏极漂移区。 具有中心开口的分流栅设置在RESURF沟槽之间的漏极漂移区的上方。 两级LDD区域设置在分裂门的中心开口下方。 接触金属叠层与三接触结构的侧面处的源极区域接触，并且在三触点结构的底表面处与主体接触区域和RESURF沟槽中的场板接触。 周边RESURF沟槽围绕着MOSFET。 外围RESURF沟槽中的场板电耦合到MOSFET的源电极。 集成缓冲器可以形成在与RESURF沟槽同时形成的沟槽中。

公开(公告)号：US08748976B1

公开(公告)日：2014-06-10

申请号：US13787044

申请日：2013-03-06

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Hideaki Kawahara ,  Hong Yang ,  Seetharaman Sridhar ,  Hao Wu ,  Boling Wen

IPC: H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0649 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802

Abstract: A semiconductor device contains a vertical MOS transistor with instances of a vertical RESURF trench on opposite sides of a vertical drift region. The vertical RESURF trench contains a dielectric trench liner on sidewalls, and a lower field plate and an upper field plate above the lower field plate. The dielectric trench liner between the lower field plate and the vertical drift region is thicker than between the upper field plate and the vertical drift region. A gate is disposed over the vertical drift region and is separate from the upper field plate. The upper field plate and the lower field plate are electrically coupled to a source electrode of the vertical MOS transistor.

Abstract translation: 半导体器件包含垂直MOS晶体管，其具有在垂直漂移区域的相对侧上的垂直RESURF沟槽的实例。 垂直RESURF沟槽包含侧壁上的电介质沟槽衬垫，下场板上的下场板和上场板。 下场板和垂直漂移区之间的电介质沟槽衬垫比上场板和垂直漂移区之间厚。 栅极设置在垂直漂移区上方并与上场板分离。 上场板和下场板电耦合到垂直MOS晶体管的源电极。

公开(公告)号：US10811533B2

公开(公告)日：2020-10-20

申请号：US15139496

申请日：2016-04-27

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Molloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

公开(公告)号：US10553717B2

公开(公告)日：2020-02-04

申请号：US15138955

申请日：2016-04-26

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Molloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

公开(公告)号：US20170062573A1

公开(公告)日：2017-03-02

申请号：US15347325

申请日：2016-11-09

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Abstract translation: 具有源区域，体接触区域和多个具有场板的沟槽结构的垂直高压MOS晶体管，以及形成MOS晶体管的方法通过减少MOS晶体管的导通电阻来降低 沟渠。 可以通过同时接触源区域，身体接触区域和场板的金属触点来减少沟槽间距。 也可以通过增加LDD区域的尺寸的栅极来减小沟槽间距。

公开(公告)号：US20160163804A1

公开(公告)日：2016-06-09

申请号：US14563706

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/404 ,  H01L21/763 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/783 ,  H01L29/7832

Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Abstract translation: 具有源区域，体接触区域和多个具有场板的沟槽结构的垂直高压MOS晶体管，以及形成MOS晶体管的方法通过减少MOS晶体管的导通电阻来降低 沟渠。 可以通过同时接触源区域，身体接触区域和场板的金属触点来减少沟槽间距。 也可以通过增加LDD区域的尺寸的栅极来减小沟槽间距。

公开(公告)号：US20150357459A1

公开(公告)日：2015-12-10

申请号：US14299040

申请日：2014-06-09

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/78 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7804 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7811

Abstract: A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

Abstract translation: 半导体器件包括在漏极接触区域上方的垂直漂移区域，通过RESURF沟槽抵靠在相对侧上。 分离栅极设置在垂直漂移区域上。 分离栅极的第一部分是MOS晶体管的栅极，并且位于垂直漂移区域的第一侧上的MOS晶体管的主体上方。 分离栅极的第二部分是沟道二极管的栅极，并且位于垂直漂移区域的第二相对侧上的沟道二极管的主体上方。 源电极电耦合到沟道二极管的源极区域和MOS晶体管的源极区域。

公开(公告)号：US11444191B2

公开(公告)日：2022-09-13

申请号：US16990284

申请日：2020-08-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.