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    Dual-port negative level sensitive data retention latch
    33.
    发明授权
    Dual-port negative level sensitive data retention latch 有权
    双端口负电平敏感数据保持锁存器

    公开(公告)号：US09013217B2

    公开(公告)日：2015-04-21

    申请号：US14311752

    申请日：2014-06-23

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: H03K3/00 ,  H03K3/356

    CPC classification number: H03K3/356008

    Abstract: In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

    Abstract translation: 在本发明的一个实施例中，双端口负电平敏感数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟输入。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和控制信号SS和SSN。 信号CKT，CLKZ，RET，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

    Nonvolatile logic array with built-in test result signal
    34.
    发明授权
    Nonvolatile logic array with built-in test result signal 有权
    具有内置测试结果信号的非易失性逻辑阵列

    公开(公告)号：US08897088B2

    公开(公告)日：2014-11-25

    申请号：US13753771

    申请日：2013-01-30

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G11C29/50 ,  G11C29/08 ,  G11C29/34 ,  G11C11/401 ,  G11C29/02

    CPC classification number: G11C29/08 ,  G11C11/22 ,  G11C11/401 ,  G11C14/0072 ,  G11C29/02 ,  G11C29/12 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/0401

    Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.

    Abstract translation: 片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。 每个位单元被配置为存储一位数据。 存在m个位线，每个位线耦合到位单元的m列的相应一个。 存在m个写入驱动器，每个写入驱动器耦合到m个位线中的相应一个位线。 与门耦合到m位线，并且具有耦合到SoC上的测试控制器的输入的输出线。 OR门耦合到m位线，并且具有耦合到测试控制器的输入的输出线。

    Four Capacitor Nonvolatile Bit Cell
    35.
    发明申请
    Four Capacitor Nonvolatile Bit Cell 有权
    四电容非易失位单元

    公开(公告)号：US20140211532A1

    公开(公告)日：2014-07-31

    申请号：US13753782

    申请日：2013-01-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G11C11/22

    CPC classification number: G11C11/221

    Abstract: A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed.

    Abstract translation: 片上系统（SoC）提供了非易失性位单元的存储器阵列。 每个位单元包括在第一板线和第二板线之间串联连接的两个铁电电容器，使得在两个铁电电容器之间形成节点Q。 第一板线和第二板线配置成在位单元未被访问时提供大致等于第一电压的电压。 钳位电路耦合到节点Q并且可操作以在不访问位单元的情况下将节点Q钳位到大致等于第一电压的电压。

    Boot State Restore from Nonvolatile Bitcell Array
    36.
    发明申请
    Boot State Restore from Nonvolatile Bitcell Array 审中-公开
    从非易失位单元阵列启动状态恢复

    公开(公告)号：US20140075174A1

    公开(公告)日：2014-03-13

    申请号：US13770041

    申请日：2013-02-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F9/44

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A processing device using a plurality of volatile storage elements to execute a boot process for and stores in a plurality of non-volatile logic element arrays a boot state representing a state of the processing device after a given amount of the boot process is completed. When it is determined that the processing device needs to restart from a boot state, energy can be saved by restoring the machine state at that boot state instead of re-booting. The stored boot state will not change, and given the nature of certain non-volatile storage elements, the data read from the NVL storage elements needs to be re-written to the elements after read out. Accordingly, a round-trip data restoration operation is executed that automatically writes back data to an individual non-volatile logic element after reading data from the individual non-volatile logic element without completing separate read and write operations.

    Abstract translation: 一种处理装置，其使用多个易失性存储元件来执行引导处理并且在多个非易失性逻辑元件阵列中存储表示在给定量的引导处理之后处理装置的状态的引导状态。 当确定处理设备需要从引导状态重新启动时，可以通过在引导状态下恢复机器状态而不是重新引导来节省能量。 存储的启动状态不会改变，并且鉴于某些非易失性存储元件的性质，从NVL存储元件读取的数据需要在读出后重新写入元件。 因此，执行往返数据恢复操作，其在从单独的非易失性逻辑元件读取数据之后自动将数据写回单个非易失性逻辑元件，而不完成单独的读取和写入操作。

    Priority Based Backup in Nonvolatile Logic Arrays
    37.
    发明申请
    Priority Based Backup in Nonvolatile Logic Arrays 有权
    非易失逻辑阵列中基于优先级的备份

    公开(公告)号：US20140075087A1

    公开(公告)日：2014-03-13

    申请号：US13770004

    申请日：2013-02-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F3/06

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.

    Abstract translation: 处理设备基于优先级或合并结构有选择地仅备份某些数据。 在一种方法中，非易失性逻辑控制器通过将表示机器状态的数据的一部分存储在非易失性逻辑元件阵列中而不是机器状态的所有数据来存储机器状态。 因此，非易失性逻辑控制器通过根据用于备份和恢复的第一类别存储机器状态的第一组程序数据来存储多个非易失性逻辑单元阵列中的机器状态，并存储第二组程序 根据用于备份和恢复的第二类别的机器状态的数据。

    COMPUTE THROUGH POWER LOSS HARDWARE APPROACH FOR PROCESSING DEVICE HAVING NONVOLATILE LOGIC MEMORY
    39.
    发明申请
    COMPUTE THROUGH POWER LOSS HARDWARE APPROACH FOR PROCESSING DEVICE HAVING NONVOLATILE LOGIC MEMORY 有权

    公开(公告)号：US20210373647A1

    公开(公告)日：2021-12-02

    申请号：US17404125

    申请日：2021-08-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F1/3293 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/07

    Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

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