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31.发明申请公开(公告)号：US20180131545A1
公开(公告)日：2018-05-10
申请号：US15860988
申请日：2018-01-03
Applicant: Texas Instruments Incorporated
CPC classification number: H04L27/22 , H03D3/00 , H03K19/21 , H03L7/081 , H03L7/087 , H03L7/113 , H04L7/0087 , H04L7/0331 , H04L27/2271
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.
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公开(公告)号：US20170353157A1
公开(公告)日：2017-12-07
申请号：US15173044
申请日：2016-06-03
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Kumar Anurag Shrivastava , Madhulatha Bonu
CPC classification number: H03B5/06 , H03B5/04 , H03B5/1221 , H03B5/1234 , H03L3/00 , H03L7/00
Abstract: Methods and apparatus are disclosed to generate an oscillating output signal having a voltage swing greater than a voltage swing across nodes of active devices. An example oscillator includes a tank to generate an oscillating output signal in response receiving an edge of an enable signal; a feedback generator including a first gain stage forming a first feedback loop with the tank, the first feedback loop providing a first charge to maintain the oscillating output signal and a second gain stage forming a second feedback loop with the tank, the second feedback loop providing a second charge to maintain the oscillating output signal, the first and second charges combining with the oscillating output signal to generate a high voltage swing; and an attenuator connected between the tank and the feedback generator to isolate the tank from active components of the feedback generator.
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公开(公告)号：US20170343589A1
公开(公告)日：2017-11-30
申请号：US15163380
申请日：2016-05-24
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Anoop Narayan Bhat
IPC: G01R19/04
CPC classification number: G01R19/04 , H03D1/2272 , H03D1/229
Abstract: A reduced-stage feedback-based envelope detector includes, for example, an input rectifier for rectifying a received modulated input signal and an amplifier for receiving the rectified modulated input signal at an input node. The amplifier compares the rectified modulated input signal with a reference signal, filters the rectified modulated input signal at the input node, and generates an envelope detection signal in response to the comparison and the filtering of the rectified modulated input signal. In an embodiment, the gain of the amplifier is independently determined from the bandwidth of the amplifier.
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公开(公告)号：US09601995B1
公开(公告)日：2017-03-21
申请号：US15145775
申请日：2016-05-03
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Kumar Anurag Shrivastava
IPC: G01R19/00 , H02M3/07 , H03K3/0233 , H03K17/22
CPC classification number: H03K3/02337 , G01R19/04 , H03K9/02
Abstract: A low power radio frequency envelope detector includes a charging transistor for controlling the charge supplied to an output capacitor. A first input capacitor couples an input signal to a gate of the charging transistor. A second input capacitor couples a first polarity of the input signal to a first diode such that the first diode is operable to couple charge to the first input capacitor and to the gate of the charging transistor in response to a positive excursion of the first polarity of the input signal. A third input capacitor couples a second polarity of the input signal to a second diode coupled in series with the first diode. The first and second diodes are operable to couple charge to the first input capacitor and to the gate of the charging transistor in response to a positive excursion of the first polarity of the input signal.
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公开(公告)号：US12189549B2
公开(公告)日：2025-01-07
申请号：US18126602
申请日：2023-03-27
Applicant: Texas Instruments Incorporated
Inventor： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
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Patent Agency Ranking
公开(公告)号：US20240235564A9
公开(公告)日：2024-07-11
申请号：US18081028
申请日：2022-12-14
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Yogesh Darwhekar
CPC classification number: H03M1/0604 , H03K21/026
Abstract: A digital-to-time converter (DTC) circuit. The DTC circuit includes a charge node. A variable current source has a source input and a source output. The source input is coupled to a DTC digital input and the source output is coupled to the charge node. A capacitor has a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the charge node. A comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is coupled to the charge node, the second comparator input is coupled to a reference voltage terminal, and the comparator output is coupled to a DTC output. A pre-charge circuit has a pre-charge control input and a pre-charge output. The pre-charge control input is coupled to a DTC pre-charge input and the pre-charge output is coupled to the capacitor.
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37.发明申请公开(公告)号：US20210249336A1
公开(公告)日：2021-08-12
申请号：US17242121
申请日：2021-04-27
Applicant: Texas Instruments Incorporated
Inventor： Benjamin Michael Sutton , Sreenivasan K. Koduri , Subhashish Mukherjee
IPC: H01L23/495
Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.
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38.发明申请公开(公告)号：US20200313945A1
公开(公告)日：2020-10-01
申请号：US16900010
申请日：2020-06-12
Applicant: Texas Instruments Incorporated
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.
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公开(公告)号：US10447202B2
公开(公告)日：2019-10-15
申请号：US15427856
申请日：2017-02-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.
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公开(公告)号：US10382078B2
公开(公告)日：2019-08-13
申请号：US15486909
申请日：2017-04-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Yogesh Darwhekar , Nagaraj V. Dixit , Raghu Ganesan
IPC: H04B1/10 , H04B1/16 , H04B17/318 , H03L7/099 , H03J7/00 , H03L7/087 , H03L7/18 , H04B1/12 , H03G3/30
Abstract: At least some embodiments are directed to a receiver system that comprises a first oscillation module configured to provide oscillating signals of differing frequencies and a second oscillation module configured to provide other oscillating signals of the differing frequencies. The second oscillation module is configured to produce less noise than the first oscillation module. A controller is coupled to the first and second oscillation modules and configured to selectively activate and deactivate each of the first and second oscillation modules based on signal strengths of primary signals received via a wireless medium and based on signal strengths of interference signals received via the wireless medium.
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