公开(公告)号：US11074944B2

公开(公告)日：2021-07-27

申请号：US16502852

申请日：2019-07-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumitaka Arai ,  Keiji Hosotani ,  Nobuyuki Momo

IPC: G11C5/06 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11524 ,  G11C16/10 ,  G11C16/30 ,  H01L27/11519 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes: first to fifth interconnects; a semiconductor layer having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect; a memory cell; a conductive layer having one end connected to the second interconnect and other end connected to the semiconductor layer; a first insulating layer provided to extend between the third and fourth interconnects and the semiconductor layer, and between the fifth interconnect and the conductive layer; an oxide semiconductor layer provided to extend between the fourth and fifth interconnects and the first insulating layer; and a second insulating layer provided to extend between the fourth and fifth interconnects and the oxide semiconductor layer.

公开(公告)号：US11018148B2

公开(公告)日：2021-05-25

申请号：US15704758

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Yuta Watanabe ,  Fumitaka Arai ,  Katsuyuki Sekine ,  Toshiyuki Iwamoto ,  Wataru Sakamoto ,  Tatsuya Kato

IPC: H01L27/11556 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  H01L21/311 ,  H01L29/10 ,  H01L21/285 ,  H01L21/3065

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.

公开(公告)号：US10763272B2

公开(公告)日：2020-09-01

申请号：US15929102

申请日：2019-02-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru Sakamoto ,  Ryota Suzuki ,  Tatsuya Okamoto ,  Tatsuya Kato ,  Fumitaka Arai

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L29/66 ,  H01L29/792 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/06

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

公开(公告)号：US10650894B2

公开(公告)日：2020-05-12

申请号：US16296100

申请日：2019-03-07

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Yusuke Shimada ,  Fumitaka Arai

IPC: G11C16/26 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer provided above the third conductive layer, the fifth conductive layer being spaced apart from the third conductive layer in the first direction, and the fifth conductive layer being provided parallel to the substrate plane, a sixth conductive layer provided above the fourth conductive layer, the sixth conductive layer being spaced apart from the fourth conductive layer in the first direction, and the sixth conductive layer being provided parallel to the substrate plane, an insulator provided between the first and second conductive layers, between the third and fourth conductive layers, and between the fifth and sixth conductive layers, a first signal line provided between the first, third, and fifth conductive layers and the insulator, the first signal line extending in the first direction, a second signal line provided between the second, fourth, and sixth conductive layers and the insulator, the second signal line extending in the first direction, a first memory cell provided between the first conductive layer and the first signal line, the first memory cell being configured to store first information, a second memory cell provided between the second conductive layer and the second signal line, the second memory cell being configured to store second information, a third memory cell provided between the third conductive layer and the first signal line, the third memory cell being configured to store third information, a fourth memory cell provided between the fourth conductive layer and the second signal line, the fourth memory cell being configured to store fourth information, a fifth memory cell provided between the fifth conductive layer and the first signal line, the fifth memory cell being configured to store fifth information, a sixth memory cell provided between the sixth conductive layer and the second signal line, the sixth memory cell being configured to store sixth information, and a control circuit configured to apply a second voltage to the third conductive layer, the control circuit being configured to apply a third voltage to the fifth conductive layer, the control circuit being configured to read data from the first memory cell, the second voltage being smaller than a first voltage, the first voltage being applied to the first conductive layer, and the third voltage being larger than the first voltage.

公开(公告)号：US10553601B2

公开(公告)日：2020-02-04

申请号：US16041460

申请日：2018-07-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura ,  Tomoaki Sawabe

IPC: H01L27/11568 ,  G11C16/04 ,  H01L29/66 ,  G11C5/06 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L29/792

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

公开(公告)号：US10541311B2

公开(公告)日：2020-01-21

申请号：US15263459

申请日：2016-09-13

Applicant: Toshiba Memory Corporation

Inventor： Katsuyuki Sekine ,  Tatsuya Kato ,  Fumitaka Arai ,  Toshiyuki Iwamoto ,  Yuta Watanabe ,  Atsushi Murakoshi

IPC: H01L29/423 ,  H01L27/115 ,  H01L23/528 ,  H01L21/28 ,  H01L27/11556 ,  H01L21/285 ,  H01L21/768

Abstract: In a semiconductor memory device, first insulating films are arranged along a first direction and a second direction and extend in a third direction. Interconnect is disposed between the first insulating films in the first direction and extends in the third direction. Electrodes are disposed between the first insulating films in the first direction on a second direction side of the interconnect, and is arranged along the third direction. Second insulating film is disposed between the interconnect and the electrodes. Semiconductor members are arranged along the third direction between the first insulating films in the second direction and extend in the first direction. The electrode is disposed between the interconnect and the semiconductor members. Third insulating film is disposed between the electrodes and the semiconductor member and is thicker than the second insulating film.

公开(公告)号：US10418376B2

公开(公告)日：2019-09-17

申请号：US15819003

申请日：2017-11-21

Applicant: Toshiba Memory Corporation

Inventor： Koichi Sakata ,  Yuta Watanabe ,  Keisuke Kikutani ,  Satoshi Nagashima ,  Fumitaka Arai ,  Toshiyuki Iwamoto

IPC: H01L27/11582 ,  H01L27/1156 ,  H01L21/28 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.

公开(公告)号：US20190181151A1

公开(公告)日：2019-06-13

申请号：US16276026

申请日：2019-02-14

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Wataru Sakamoto ,  Fumitaka Arai

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11548

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

公开(公告)号：US10276586B2

公开(公告)日：2019-04-30

申请号：US15254014

申请日：2016-09-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Atsushi Murakoshi ,  Yasuhito Yoshimizu ,  Tomofumi Inoue ,  Tatsuya Kato ,  Yuta Watanabe ,  Fumitaka Arai

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/28

Abstract: According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.

公开(公告)号：US10074667B1

公开(公告)日：2018-09-11

申请号：US15688561

申请日：2017-08-28

Applicant: Toshiba Memory Corporation

Inventor： Kazuyuki Higashi ,  Kazumichi Tsumura ,  Ryota Katsumata ,  Fumitaka Arai

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L25/065 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11553 ,  H01L27/11563 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/788

Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.