公开(公告)号：US10304851B2

公开(公告)日：2019-05-28

申请号：US15909494

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi Nakaki ,  Yosuke Mitsuno ,  Tatsuya Okamoto

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/10 ,  H01L29/51 ,  H01L29/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11568 ,  H01L23/528 ,  H01L23/522 ,  H01L21/265 ,  H01L29/167 ,  H01L21/28

Abstract: A semiconductor memory device includes a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate, a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region, a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region, a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region, a second semiconductor pillar extending in the second direction through at least one electrode film in the contact region, a charge storage film between the first semiconductor pillar and each electrode film, an insulating film between the second semiconductor pillar and the at least one electrode film.

公开(公告)号：US10181477B2

公开(公告)日：2019-01-15

申请号：US15262274

申请日：2016-09-12

Applicant: Toshiba Memory Corporation

Inventor： Hirokazu Ishigaki ,  Tatsuya Okamoto ,  Masao Shingu

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/30 ,  H01L27/11568 ,  H01L21/28 ,  H01L21/02

Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.

公开(公告)号：US10763272B2

公开(公告)日：2020-09-01

申请号：US15929102

申请日：2019-02-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru Sakamoto ,  Ryota Suzuki ,  Tatsuya Okamoto ,  Tatsuya Kato ,  Fumitaka Arai

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L29/66 ,  H01L29/792 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/06

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

公开(公告)号：US09842856B2

公开(公告)日：2017-12-12

申请号：US15251438

申请日：2016-08-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tatsuya Okamoto ,  Tatsufumi Hamada

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/40 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11556

Abstract: According to an embodiment, a semiconductor memory device comprises: a plurality of control gate electrodes stacked above a substrate; a first semiconductor layer extending in a first direction above the substrate and facing the plurality of control gate electrodes; a gate insulating layer extending in the first direction and provided between the control gate electrode and first semiconductor layer; and a second semiconductor layer positioned downwardly of the first semiconductor layer and gate insulating layer, and connected to a lower end of the first semiconductor layer and the substrate. Moreover, the first semiconductor layer comprises: a first portion contacting an upper surface of the second semiconductor layer at a position more downward than a lower end of the gate insulating layer; and a second portion connected to an upper end of the first portion, extending in the first direction, and having a different crystalline structure from the first portion.

公开(公告)号：US10242992B2

公开(公告)日：2019-03-26

申请号：US15205954

申请日：2016-07-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru Sakamoto ,  Ryota Suzuki ,  Tatsuya Okamoto ,  Tatsuya Kato ,  Fumitaka Arai

IPC: H01L27/115 ,  G11C16/02 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/06

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

公开(公告)号：US11018217B2

公开(公告)日：2021-05-25

申请号：US16549826

申请日：2019-08-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Ishida ,  Takahiro Sugimoto ,  Hiroshi Kanno ,  Tatsuya Okamoto

IPC: H01L29/04 ,  H01L21/8234 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11568

Abstract: A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.

公开(公告)号：US09754954B2

公开(公告)日：2017-09-05

申请号：US15201708

申请日：2016-07-05

Applicant: Toshiba Memory Corporation

Inventor： Masaaki Higuchi ,  Katsuyuki Sekine ,  Fumiki Aiso ,  Takuo Ohashi ,  Tatsuya Okamoto

IPC: H01L27/115 ,  H01L27/11556 ,  H01L29/778 ,  H01L21/02 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7785

Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.