公开(公告)号：US11024719B2

公开(公告)日：2021-06-01

申请号：US16563307

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoaki Sawabe ,  Nobuyoshi Saito ,  Junji Kataoka ,  Tomomasa Ueda ,  Keiji Ikeda

IPC: H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L27/24 ,  H01L29/78

Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.

公开(公告)号：US10553601B2

公开(公告)日：2020-02-04

申请号：US16041460

申请日：2018-07-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura ,  Tomoaki Sawabe

IPC: H01L27/11568 ,  G11C16/04 ,  H01L29/66 ,  G11C5/06 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L29/792

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

公开(公告)号：US10714629B2

公开(公告)日：2020-07-14

申请号：US16122834

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Nobuyoshi Saito ,  Tomomasa Ueda ,  Kentaro Miura ,  Keiji Ikeda ,  Tsutomu Tezuka

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66 ,  H01L21/02

Abstract: According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.

公开(公告)号：US10950735B2

公开(公告)日：2021-03-16

申请号：US16351245

申请日：2019-03-12

Applicant: Toshiba Memory Corporation

Inventor： Junji Kataoka ,  Tomomasa Ueda ,  Tomoaki Sawabe ,  Keiji Ikeda ,  Nobuyoshi Saito

IPC: H01L29/786 ,  H01L45/00 ,  H01L29/24

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.

公开(公告)号：US10790396B2

公开(公告)日：2020-09-29

申请号：US16103880

申请日：2018-08-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoaki Sawabe ,  Tomomasa Ueda ,  Keiji Ikeda ,  Tsutomu Tezuka ,  Nobuyoshi Saito

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/108 ,  H01L29/778 ,  H01L21/44 ,  H01L21/4763

Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.

公开(公告)号：US20180269217A1

公开(公告)日：2018-09-20

申请号：US15698077

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Kentaro MIURA ,  Tomomasa Ueda ,  Keiji Ikeda ,  Nobuyoshi Saito

IPC: H01L27/11524 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/11524 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/786

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

公开(公告)号：US10312239B2

公开(公告)日：2019-06-04

申请号：US15704643

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  H01L27/12 ,  H01L27/108 ,  H01L29/786 ,  H01L27/1156 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

公开(公告)号：US10192876B2

公开(公告)日：2019-01-29

申请号：US15698077

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Kentaro Miura ,  Tomomasa Ueda ,  Keiji Ikeda ,  Nobuyoshi Saito

IPC: H01L27/00 ,  H01L27/11524 ,  H01L27/12 ,  H01L29/786

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

公开(公告)号：US20180269210A1

公开(公告)日：2018-09-20

申请号：US15704643

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu TEZUKA ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/10802 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  H01L27/10847 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

公开(公告)号：US10043808B1

公开(公告)日：2018-08-07

申请号：US15705457

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: H01L29/76 ,  H01L27/105 ,  H01L29/792 ,  H01L29/786 ,  G11C11/4097 ,  H01L29/423

Abstract: According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a gate insulating film on a semiconductor layer; an oxide semiconductor layer above the semiconductor layer; a first control gate of a first cell and a second control gate of a second cell on an insulating layer on the oxide semiconductor layer; a third gate of a first transistor between the first control gate and the second control gate; a fourth gate of a second transistor between a first end of the oxide semiconductor layer and the second control gate; an interconnect connected to the first end; a source line connected to the first select transistor; and a bit line connected to the second select transistor.