公开(公告)号：US11183507B2

公开(公告)日：2021-11-23

申请号：US15682996

申请日：2017-08-22

Applicant: Toshiba Memory Corporation

Inventor： Katsuyuki Sekine ,  Tatsuya Kato ,  Fumitaka Arai ,  Toshiyuki Iwamoto ,  Yuta Watanabe ,  Wataru Sakamoto ,  Hiroshi Itokawa ,  Akio Kaneko

IPC: H01L27/11556 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H01L29/788 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/311 ,  H01L27/11519 ,  H01L29/10 ,  H01L29/49

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

公开(公告)号：US11011541B2

公开(公告)日：2021-05-18

申请号：US16559389

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke Nakatsuka ,  Fumitaka Arai

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/14 ,  G11C16/10 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/26

Abstract: A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.

公开(公告)号：US10833103B2

公开(公告)日：2020-11-10

申请号：US16563627

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Haruka Sakuma ,  Hidenori Miyagawa ,  Shosuke Fujii ,  Kiwamu Sakuma ,  Fumitaka Arai

IPC: G11C11/22 ,  H01L27/11597 ,  H01L29/51 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

公开(公告)号：US10650900B2

公开(公告)日：2020-05-12

申请号：US15923501

申请日：2018-03-16

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke Shimada ,  Fumitaka Arai ,  Tatsuya Kato

IPC: G11C16/26 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.

公开(公告)号：US10438959B2

公开(公告)日：2019-10-08

申请号：US16012285

申请日：2018-06-19

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Atsushi Murakoshi ,  Fumitaka Arai

IPC: H01L29/76 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548

Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.

公开(公告)号：US20180269218A1

公开(公告)日：2018-09-20

申请号：US15704667

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya KATO ,  Fumitaka Arai ,  Kohei Sakaike ,  Satoshi Nagashima

IPC: H01L27/11524 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/1156 ,  H01L27/11541

CPC classification number: H01L27/11524 ,  H01L27/11541 ,  H01L27/11556 ,  H01L27/1156 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.

公开(公告)号：US10020315B1

公开(公告)日：2018-07-10

申请号：US15705514

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Atsushi Murakoshi ,  Fumitaka Arai

IPC: H01L29/76 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556

Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.

公开(公告)号：US10312239B2

公开(公告)日：2019-06-04

申请号：US15704643

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  H01L27/12 ,  H01L27/108 ,  H01L29/786 ,  H01L27/1156 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

公开(公告)号：US10249635B2

公开(公告)日：2019-04-02

申请号：US15822860

申请日：2017-11-27

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Wataru Sakamoto ,  Fumitaka Arai

IPC: H01L27/11519 ,  H01L27/11556 ,  H01L27/11548

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

公开(公告)号：US10242992B2

公开(公告)日：2019-03-26

申请号：US15205954

申请日：2016-07-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru Sakamoto ,  Ryota Suzuki ,  Tatsuya Okamoto ,  Tatsuya Kato ,  Fumitaka Arai

IPC: H01L27/115 ,  G11C16/02 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/06

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.