公开(公告)号：US09865612B2

公开(公告)日：2018-01-09

申请号：US15263832

申请日：2016-09-13

Applicant: Toshiba Memory Corporation

Inventor： Shinya Arai

IPC: H01L29/792 ,  H01L27/11568 ,  H01L21/28 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11553 ,  H01L27/11551

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  H01L21/28282 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11568 ,  H01L28/00

Abstract: A semiconductr memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

公开(公告)号：US09761606B1

公开(公告)日：2017-09-12

申请号：US15266850

申请日：2016-09-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Ishida ,  Jun Fujiki ,  Shinya Arai ,  Fumitaka Arai ,  Hideaki Aochi ,  Kotaro Fujii

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11578

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.