公开(公告)号：US20190355742A1

公开(公告)日：2019-11-21

申请号：US16296276

申请日：2019-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki MARUYAMA ,  Yoshiaki Fukuzumi ,  Yuki Sugiura ,  Shinya Arai ,  Fumie Kikushima ,  Keisuke Suda ,  Takashi Ishida

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/768

Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.

公开(公告)号：US11251193B2

公开(公告)日：2022-02-15

申请号：US16558725

申请日：2019-09-03

Applicant: Toshiba Memory Corporation

Inventor： Ken Komiya ,  Takashi Ishida ,  Hiroshi Kanno

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/74 ,  H01L29/10 ,  H01L27/1157

Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.

公开(公告)号：US10916562B2

公开(公告)日：2021-02-09

申请号：US16411307

申请日：2019-05-14

Applicant: Toshiba Memory Corporation

Inventor： Takashi Ishida ,  Yoshiaki Fukuzumi ,  Takayuki Okada ,  Masaki Tsuji

IPC: H01L23/48 ,  H01L23/52 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/423

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

公开(公告)号：US10340285B2

公开(公告)日：2019-07-02

申请号：US15928951

申请日：2018-03-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Ishida ,  Yoshiaki Fukuzumi ,  Takayuki Okada ,  Masaki Tsuji

IPC: H01L23/48 ,  H01L23/52 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/423

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

公开(公告)号：US09997535B2

公开(公告)日：2018-06-12

申请号：US15237984

申请日：2016-08-16

Applicant: Toshiba Memory Corporation

Inventor： Takashi Ishida

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/0223 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L28/00 ,  H01L29/4991 ,  H01L29/511 ,  H01L29/517

Abstract: According to an embodiment, a semiconductor memory device comprises: control gate electrodes stacked above a substrate; a semiconductor layer that extends in a first direction above the substrate and faces the control gate electrodes; and a gate insulating layer provided between these control gate electrode and semiconductor layer. The gate insulating layer comprises: a first insulating layer covering a side surface of the semiconductor layer; a charge accumulation layer covering a side surface of this first insulating layer; and a second insulating layer including a metal oxide and covering a side surface of this charge accumulation layer. The charge accumulation layer has: a first portion facing the control gate electrode; and a second portion facing a region between control gate electrodes adjacent in the first direction and including more oxygen than the first portion.

公开(公告)号：US11018217B2

公开(公告)日：2021-05-25

申请号：US16549826

申请日：2019-08-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Ishida ,  Takahiro Sugimoto ,  Hiroshi Kanno ,  Tatsuya Okamoto

IPC: H01L29/04 ,  H01L21/8234 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11568

Abstract: A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.

公开(公告)号：US10658295B2

公开(公告)日：2020-05-19

申请号：US16126064

申请日：2018-09-10

Applicant: Toshiba Memory Corporation

Inventor： Tomoya Kawai ,  Takashi Ishida ,  Shuichi Toriyama

IPC: H01L23/532 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/14 ,  H01L27/1157 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect layer, a first insulating layer, a second interconnect layer, and a memory pillar including a second insulating layer, a charge storage layer, and a third insulating layer stacked on a part of a side surface and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer stacked in order along a first direction. A height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.

公开(公告)号：US10283647B2

公开(公告)日：2019-05-07

申请号：US15669397

申请日：2017-08-04

Applicant: Toshiba Memory Corporation

Inventor： Koji Matsuo ,  Gaku Sudo ,  Jun Nogami ,  Tatsuro Shinozaki ,  Takashi Ishida ,  Jun Fujiki ,  Kenzo Manabe

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11578 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/16 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.

公开(公告)号：US09934860B1

公开(公告)日：2018-04-03

申请号：US15453058

申请日：2017-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Ishida

IPC: G11C16/06 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0466 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor memory device includes first to fourth electrodes; first and second semiconductor members; a first charge storage member provided between the first semiconductor member and the first electrode; a first interconnect connected to the second electrode side of the first semiconductor member and to the fourth electrode side of the second semiconductor member; and a control circuit. The control circuit sets the first interconnect to a floating state, causes a potential of the third electrode side of the second semiconductor member to increase to a first potential, causes the potential of the third electrode to increase to a second potential lower than the first potential, causes the potential of the second electrode to increase to a third potential lower than the first potential, applies a fourth potential lower than the second and the third potentials to the first electrode, and sets the fourth electrode to a floating state.

公开(公告)号：US09761606B1

公开(公告)日：2017-09-12

申请号：US15266850

申请日：2016-09-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Ishida ,  Jun Fujiki ,  Shinya Arai ,  Fumitaka Arai ,  Hideaki Aochi ,  Kotaro Fujii

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11578

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.