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    Semiconductor memory device realizing high speed access and low power consumption with redundant circuit
    31.
    发明授权
    Semiconductor memory device realizing high speed access and low power consumption with redundant circuit 失效
    半导体存储器件利用冗余电路实现高速存取和低功耗

    公开(公告)号：US5798974A

    公开(公告)日：1998-08-25

    申请号：US721075

    申请日：1996-09-26

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/808 ,  G11C29/832 ,  G11C29/842

    摘要： If a row (column) redundant circuit is not used, a comparison between a defective address and an internal address is not performed in a row (column) fuse programming portion in accordance with a signal output from a circuit for indicating if a row (column) redundant circuit is to be used or not. A comparison outcome signal which is generated when these addresses do not match each other is to be output from the row (column) fuse programming portion.

    摘要翻译： 如果不使用行（列）冗余电路，则根据从电路输出的信号，在行（列）熔丝编程部分中不执行缺陷地址和内部地址之间的比较，用于指示行（列） ）冗余电路是否被使用。 当这些地址彼此不匹配时产生的比较结果信号将从行（列）熔丝编程部分输出。

    Static type semiconductor device operable at a low voltage with small power consumption
    32.
    发明授权
    Static type semiconductor device operable at a low voltage with small power consumption 失效
    静态型半导体器件可在低电压下工作，功耗小

    公开(公告)号：US5677889A

    公开(公告)日：1997-10-14

    申请号：US517030

    申请日：1995-08-18

    申请人： Yoshiyuki Haraguchi ,  Tadato Yamagata

    发明人： Yoshiyuki Haraguchi ,  Tadato Yamagata

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  G11C11/412 ,  G11C11/417 ,  G11C7/00

    CPC分类号： G11C5/14 ,  G11C11/412 ,  G11C11/417

    摘要： An SRAM includes a memory cell array, a peripheral circuitry including a bit line load connected to the memory cell array, a multiplexer and the like, and a voltage lowering circuit. The voltage lowering circuit receives a power supply potential Vcc and outputs a potential Vin which is lower. The potential Vin is applied to the peripheral circuitry except the memory cell array, and the power supply potential Vcc is directly applied to the memory cell array. Therefore, operational potential of the memory cell array is made relatively higher with respect to the peripheral circuitry. As a result, a static semiconductor memory device which can operation at low voltage and consumes less power can be provided.

    摘要翻译： SRAM包括存储单元阵列，包括连接到存储单元阵列的位线负载，多路复用器等的外围电路和降压电路。 电压降低电路接收电源电位Vcc并输出较低的电位Vin。 将电位Vin施加到除了存储单元阵列之外的外围电路，并且将电源电位Vcc直接施加到存储单元阵列。 因此，存储单元阵列的操作电位相对于外围电路相对较高。 结果，可以提供能够在低电压下操作并且消耗较少功率的静态半导体存储器件。

    Electric fuse for a redundancy circuit
    33.
    发明授权
    Electric fuse for a redundancy circuit 失效
    电熔丝用于冗余电路

    公开(公告)号：US4984054A

    公开(公告)日：1991-01-08

    申请号：US481683

    申请日：1990-02-20

    申请人： Michihiro Yamada ,  Hiroshi Miyamoto ,  Tadato Yamagata ,  Shigeru Mori

    发明人： Michihiro Yamada ,  Hiroshi Miyamoto ,  Tadato Yamagata ,  Shigeru Mori

    IPC分类号： H01L21/82 ,  H01H37/76 ,  H01L21/3205 ,  H01L23/525 ,  H01L27/10

    CPC分类号： H01L23/5256 ,  H01L2924/0002

    摘要： The present invention comprises a field oxide film formed on a silicon substrate, an underlying film of polycrystal silicon formed on a portion thereof and an insulating film formed so as to cover the field oxide film comprising the underlying film. A surface stepped portion of the insulating film is formed by a portion with an underlying film and a portion without an underlying film under the insulating film, and a blowout portion of a fuse is formed along the surface stepped portion. There are terminal portions at both ends of the blowout portion of the fuse and an aluminum line is connected thereto. In addition, the whole portions comprising the fuse portion are covered with another insulating film and the whole is protected. The fuse is employed as one example in a redundancy circuit of a MOS dynamic RAM having redundancy memory cells.

    摘要翻译： 本发明包括形成在硅衬底上的场氧化物膜，形成在其一部分上的多晶硅的下面的膜和形成为覆盖包括下面的膜的场氧化物膜的绝缘膜。 绝缘膜的表面阶梯部分由具有下面的膜的部分和在绝缘膜下方没有下面的膜的部分形成，并且沿表面台阶形成熔丝的吹出部分。 在保险丝的吹出部分的两端有端子部分，铝线连接到其上。 此外，包括熔丝部分的整个部分被另一绝缘膜覆盖，并且整体被保护。 在具有冗余存储单元的MOS动态RAM的冗余电路中采用熔丝作为一个例子。

    Substrate bias circuit having substrate bias voltage clamp and operating method therefor
    34.
    发明授权
    Substrate bias circuit having substrate bias voltage clamp and operating method therefor 失效
    具有衬底偏置电压钳的衬底偏置电路及其操作方法

    公开(公告)号：US4904885A

    公开(公告)日：1990-02-27

    申请号：US204126

    申请日：1988-06-06

    申请人： Michihiro Yamada ,  Hiroshi Miyamoto ,  Tadato Yamagata ,  Shigeru Mori ,  Tetsuya Aono

    发明人： Michihiro Yamada ,  Hiroshi Miyamoto ,  Tadato Yamagata ,  Shigeru Mori ,  Tetsuya Aono

    IPC分类号： G11C11/407 ,  G05F3/20 ,  G11C11/4074 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K19/094

    CPC分类号： G11C11/4074 ,  G05F3/205

    摘要： A substrate bias circuit controls application of a conventional substrate charge pump to the substrate of a semiconductor integrated circuit to prevent latching up of parasitic transistors at the time of turn on of power to the integrated circuit. The substrate bias circuit comprises a filed effect transistor having its source and drain electrodes connected between substrate and charge pump. The gate electrode of the transistor is driven through an RC circuit by the power supply to turn on the transistor for a predetermined time period at the time power is initially applied to the integrated circuit. There is no latching up of the parasitic transistors because application of positive bias voltage to the substrate during turn-on is prevented.

    摘要翻译： 衬底偏置电路控制将常规衬底电荷泵施加到半导体集成电路的衬底，以防止在集成电路接通电源时寄生晶体管的锁存。 衬底偏置电路包括场效应晶体管，其源极和漏极连接在衬底和电荷泵之间。 晶体管的栅极通过电源通过RC电路驱动，以在初始施加到集成电路的时间将晶体管导通预定时间段。 寄生晶体管没有锁存，因为防止了在接通期间向衬底施加正偏置电压。

    SEMICONDUCTOR DEVICE
    37.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20120075029A1

    公开(公告)日：2012-03-29

    申请号：US13191076

    申请日：2011-07-26

    申请人： Yasushi SEKINE ,  Tadato Yamagata

    发明人： Yasushi SEKINE ,  Tadato Yamagata

    IPC分类号： H03B5/12 ,  H01L25/00 ,  H01C7/00

    CPC分类号： H01L28/24 ,  H01L27/016 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a semiconductor device having resistance elements small in temperature dependence of the resistance value. The semiconductor device has metal resistance element layers. The metal resistance element layer includes a resistance film layer. The other metal resistance element layer includes another metal resistance film layer. The metal resistance film layer is one of titanium nitride resistance and tantalum nitride resistance. The other metal resistance film layer is the other of the titanium nitride resistance and the tantalum nitride resistance. The resistance value of titanium nitride resistance has a positive temperature coefficient. Whereas, the resistance value of tantalum nitride resistance has a negative temperature coefficient. A contact plug electrically couples the metal resistance film layer with the other metal resistance film layer. Therefore, the temperature coefficient of the titanium nitride resistance and the temperature coefficient of the tantalum nitride resistance cancel each other. This can reduce the temperature coefficient.

    摘要翻译： 提供了具有电阻值温度依赖性小的电阻元件的半导体器件。 半导体器件具有金属电阻元件层。 金属电阻元件层包括电阻膜层。 另一个金属电阻元件层包括另一金属电阻膜层。 金属电阻膜层是氮化钛电阻和氮化钽电阻之一。 另一个金属电阻膜层是氮化钛电阻和氮化钽电阻中的另一个。 氮化钛电阻的电阻值为正温度系数。 而氮化钽电阻的电阻值为负温度系数。 接触插塞将金属电阻膜层与另一金属电阻膜层电耦合。 因此，氮化钛电阻的温度系数和氮化钽电阻的温度系数相互抵消。 这可以降低温度系数。

    Dynamic associative memory device
    38.
    发明授权
    Dynamic associative memory device 失效
    动态关联存储器件

    公开(公告)号：US06859377B2

    公开(公告)日：2005-02-22

    申请号：US10668310

    申请日：2003-09-24

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C11/401 ,  G11C15/04 ,  G11C15/00

    CPC分类号： G11C15/043

    摘要： A dynamic associative memory device comprising memory cells each of that including: a capacitor connected to one of the bit lines through first transmission gate capable of being switched to ON by an activation of a word line, and having a cell plate supplied with a source voltage; at least one second transmission gate provided in series between the bit lines, capable of being switched to ON by a memory node potential at an opposite side of a source voltage supply-side of the capacitor; and a initializing circuit for controlling the memory node potential upon receiving a reset signal so that at least one of the second transmission gates is switched to OFF.

    摘要翻译： 一种包括存储单元的动态关联存储器件，每个存储器单元包括：通过第一传输栅极连接到位线之一的电容器，其能够通过字线的激活而被切换到导通，并且具有提供有源极电压的单元板 ; 串联地设置在位线之间的至少一个第二传输门，能够通过位于电容器的源电压电源侧的相对侧的存储器节点电位而被切换到导通; 以及初始化电路，用于在接收到复位信号时控制存储器节点电位，使得至少一个第二传输门切换到OFF。

    Semiconductor integrated circuit device having hierarchical power source arrangement
    39.
    发明授权
    Semiconductor integrated circuit device having hierarchical power source arrangement 失效
    具有分层电源布置的半导体集成电路器件

    公开(公告)号：US06643208B2

    公开(公告)日：2003-11-04

    申请号：US10347220

    申请日：2003-01-21

    申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

    发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

    IPC分类号： G11C00700

    CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

    摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in access with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

    摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 变频器作为工作电源电压VCL1和VSL2或电压VCL2和VSL1，在待机周期和激活循环中的输出信号的逻辑电平进行访问。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

    Semiconductor integrated circuit device having hierarchical power source arrangement
    40.
    发明授权
    Semiconductor integrated circuit device having hierarchical power source arrangement 有权
    具有分层电源布置的半导体集成电路器件

    公开(公告)号：US06246625B1

    公开(公告)日：2001-06-12

    申请号：US09497199

    申请日：2000-02-03

    申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

    发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

    IPC分类号： G11C700

    CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

    摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

    摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 根据待机周期和激活周期中的输出信号的逻辑电平，变频器作为电压VCL1和VSL2的工作电源电压或电压VCL2和VSL1运行。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。