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    INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS
    31.
    发明申请
    INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS 有权
    半导体器件的输入缓冲电路

    公开(公告)号：US20100039142A1

    公开(公告)日：2010-02-18

    申请号：US12540496

    申请日：2009-08-13

    申请人： JI WANG LEE ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Jae Min Jang ,  Chang Kun Park

    发明人： JI WANG LEE ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Jae Min Jang ,  Chang Kun Park

    IPC分类号： H03K5/153

    CPC分类号： H03K5/153

    摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

    摘要翻译： 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

    DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME
    33.
    发明申请
    DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME 有权
    占空比校正电路和半导体集成电路设备，包括它们

    公开(公告)号：US20090231006A1

    公开(公告)日：2009-09-17

    申请号：US12331294

    申请日：2008-12-09

    申请人： Jae Min Jang ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Chang Kun Park

    发明人： Jae Min Jang ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Chang Kun Park

    IPC分类号： H03K5/04

    CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K2005/00058

    摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

    摘要翻译： 占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号 控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发， 延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

    RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS
    35.
    发明申请
    RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
    半导体存储器接收器电路

    公开(公告)号：US20090059703A1

    公开(公告)日：2009-03-05

    申请号：US12172108

    申请日：2008-07-11

    申请人： Tae Jin Hwang ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Hae Rang Choi ,  Ji Wang Lee

    发明人： Tae Jin Hwang ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Hae Rang Choi ,  Ji Wang Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

    摘要： A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.

    摘要翻译： 本文描述了一种接收器电路，包括：第一数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，并产生第一和第二感测信号，并响应于第一和第二感测信号产生第一内部数据 第一偏移控制单元，被配置为响应于第一和第二感测信号产生第一和第二偏移信号，第一和第二偏移信号在基于第一代码确定的最大电压电平和最小电压电平之间摆动，第二偏移控制单元 数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，以产生第三和第四感测信号，并响应于第三和第四感测信号产生第二内部数据; 以及第二偏移控制单元，用于响应于第三和第四感测信号产生第三和第四偏移信号，第三和第四偏移信号在基于第二代码确定的最大电压电平和最小电压电平之间摆动，其中第一和第二偏移信号 数据确定单元被配置为响应于第三和第四偏移信号来确定第一内部数据的建立时间和保持时间，并且其中第二数据确定单元被配置为响应于确定第二内部数据的建立时间和保持时间 到第一和第二偏移信号。

    PLL circuit having loop filter and method of driving the same
    36.
    发明申请
    PLL circuit having loop filter and method of driving the same 有权
    具有环路滤波器的PLL电路及其驱动方法

    公开(公告)号：US20080068058A1

    公开(公告)日：2008-03-20

    申请号：US11822103

    申请日：2007-07-02

    申请人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Yong Ju Kim ,  Kun Woo Park ,  Jong Woon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H03L7/085 ,  H03L7/08

    CPC分类号： H03L7/093 ,  H03L7/10

    摘要： A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.

    摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，并产生上拉控制信号和下拉控制信号。 环路滤波器根据上拉和下拉控制信号抽取电压，对泵浦电压进行滤波，并输出一个控制电压。 压控振荡器接收控制信号并振荡输出时钟。 时钟分频器以预定速率分频输出时钟的频率，以产生反馈时钟。 在PLL电路中，环路滤波器包括用于补偿变化的补偿器。

    Phase detecting circuit and clock generating apparatus including the same
    39.
    发明授权
    Phase detecting circuit and clock generating apparatus including the same 有权
    相位检测电路和包括该相位检测电路的时钟发生装置

    公开(公告)号：US07949081B2

    公开(公告)日：2011-05-24

    申请号：US12026384

    申请日：2008-02-05

    申请人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H04L7/04 ,  H03L7/00

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.

    摘要翻译： 相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及 充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。

    PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME
    40.
    发明申请
    PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME 有权
    相位检测电路和时钟发生装置，包括它们

    公开(公告)号：US20090097608A1

    公开(公告)日：2009-04-16

    申请号：US12026384

    申请日：2008-02-05

    申请人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Hee Woong Song ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H04L7/00

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.

    摘要翻译： 相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及 充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。