公开(公告)号：US09893184B2

公开(公告)日：2018-02-13

申请号：US14968920

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L29/7848 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: In accordance with some embodiments of the present disclosure, a fin-FET device includes a substrate, a stack structure, a source and drain region, a sidewall insulator and a metal connector. The stack structure including a gate stack is disposed on the substrate. The source and drain region is disposed beside the stack structure. The sidewall insulator is disposed on the source and drain region. The sidewall insulator includes a bottom portion and an upper portion. An interface is formed between the bottom portion and the upper portion and the bottom portion is located between the upper portion and the source and drain region. The metal connector stacks on the source and drain region and the sidewall insulator is located between the metal connector and the stack structure.

公开(公告)号：US20180026033A1

公开(公告)日：2018-01-25

申请号：US15706760

申请日：2017-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Method for fabricating Fin field effect transistors (FinFETs) are disclosed. One of the methods includes the following steps. A first semiconductor fin, a second semiconductor fin and an insulator between the first semiconductor fin and the second semiconductor fin are formed. A first dummy gate, a second dummy gate and an opening between the first and second dummy gates are formed over the insulator, wherein the first dummy gate and the second dummy gate cross over portions of the first semiconductor fin and the second semiconductor fin respectively. A dielectric layer is formed in the opening, wherein the dielectric layer comprises an air gap therein. The first dummy gate and the second dummy gate are replaced with a first gate and a second gate, wherein the first gate and the second gate are electrically insulated by the dielectric layer comprising the air gap therein.

公开(公告)号：US09859156B2

公开(公告)日：2018-01-02

申请号：US14985157

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L21/7685 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295

Abstract: An interconnection structure includes a non-insulator structure, a dielectric structure, a conductive structure and a first dielectric protective layer. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The first dielectric protective layer is present between the conductive structure and at least one sidewall of the trench opening.

公开(公告)号：US09847330B2

公开(公告)日：2017-12-19

申请号：US15071207

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, first and second gates, an opening, first and second dielectric layers. The substrate includes first and second semiconductor fins and a trench therebetween. The insulator is disposed in the trench. The first and second gates are respectively disposed on the first and second semiconductor fins. The opening is disposed between the first gate and the second gate. The first dielectric layer is disposed in the opening to electrically insulate the first and second gates and includes a slit. The second dielectric layer is filled in the slit, wherein the opening has a first width in a direction along which the first and second gates extend, the slit has a second width in the direction, and a ratio of the first width to the second width is larger than 2.

公开(公告)号：US09818841B2

公开(公告)日：2017-11-14

申请号：US14713517

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chai-Wei Chang ,  Che-Cheng Chang ,  Po-Chi Wu ,  Yi-Cheng Chao

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/76 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/3081 ,  H01L29/42356 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over the gate dielectric layer. The gate structure further includes a gate electrode layer formed over the work function metal layer. In addition, a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer.

公开(公告)号：US09793407B2

公开(公告)日：2017-10-17

申请号：US14968906

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/785

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US09786505B2

公开(公告)日：2017-10-10

申请号：US14984555

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L21/2253 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top surface of the insulating structure is non-concave and is lower than a top surface of the active semiconductor fin. The gate electrode is disposed over the active semiconductor fin. The gate dielectric is disposed between the gate electrode and the active semiconductor fin.

公开(公告)号：US09773871B2

公开(公告)日：2017-09-26

申请号：US14941664

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/1083 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a substrate, a plurality of insulators disposed on the substrate, a gate stack and a strained material. The substrate includes at least one semiconductor fin and the semiconductor fin includes at least one modulation portion distributed therein. The semiconductor fin is sandwiched by the insulators. The gate stack is disposed over portions of the semiconductor fin and over portions of the insulators. The strained material covers portions of the semiconductor fin that are revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

公开(公告)号：US09761488B2

公开(公告)日：2017-09-12

申请号：US14802734

申请日：2015-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tai-Shin Cheng ,  Che-Cheng Chang ,  Wei-Ting Chen ,  Wei-Yin Shiao

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/76883 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/02178 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814

Abstract: A method for forming the semiconductor device structure is provided. The method includes forming a metal layer in a first dielectric layer over a substrate and forming an etch stop layer over the metal layer. The etch stop layer is made of metal-containing material. The method also includes forming a second dielectric layer over the etch stop layer and removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process. The method further includes performing a plasma cleaning process on the via and the second dielectric layer, and the plasma cleaning process is performed by using a plasma including nitrogen gas (N2) and hydrogen gas (H2).

公开(公告)号：US20170229451A1

公开(公告)日：2017-08-10

申请号：US15071207

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, first and second gates, an opening, first and second dielectric layers. The substrate includes first and second semiconductor fins and a trench therebetween. The insulator is disposed in the trench. The first and second gates are respectively disposed on the first and second semiconductor fins. The opening is disposed between the first gate and the second gate. The first dielectric layer is disposed in the opening to electrically insulate the first and second gates and includes a slit. The second dielectric layer is filled in the slit, wherein the opening has a first width in a direction along which the first and second gates extend, the slit has a second width in the direction, and a ratio of the first width to the second width is larger than 2.