公开(公告)号：US11508624B2

公开(公告)日：2022-11-22

申请号：US16938401

申请日：2020-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhe-Ching Lu ,  Bao-Ru Young ,  Yen-Sen Wang ,  Tsung-Chieh Tsai

IPC: H01L21/8238 ,  H01L27/092

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area.

公开(公告)号：US20220310583A1

公开(公告)日：2022-09-29

申请号：US17213979

申请日：2021-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung Feng Chang ,  Chun-Chia Hsu ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L27/02 ,  H01L29/08 ,  H01L27/092

Abstract: A semiconductor structure includes a substrate having first and second wells of first and second conductivity types respectively. From a top view, the first and second wells extend lengthwise along a first direction, the first and second wells each includes a protruding section that protrudes along a second direction perpendicular to the first direction and a recessed section that recedes along the second direction. The protruding section of the first well fits into the recessed section of the second well, and vice versa. The semiconductor structure further includes first source/drain features over the protruding section of the first well; second source/drain features over the second well; third source/drain features over the protruding section of the second well; and fourth source/drain features over the first well. The first and second source/drain features are of the first conductivity type. The third and fourth source/drain features are of the second conductivity type.

公开(公告)号：US20210192121A1

公开(公告)日：2021-06-24

申请号：US17195136

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Yung Feng Chang

IPC: G06F30/398 ,  G06F30/39 ,  G06F30/367 ,  G03F1/36

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

公开(公告)号：US10535746B2

公开(公告)日：2020-01-14

申请号：US16044227

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi Lee ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Chia-Sheng Fan

IPC: H01L29/49 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/84 ,  H01L29/66

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.

公开(公告)号：US10515850B2

公开(公告)日：2019-12-24

申请号：US15686336

申请日：2017-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung Wang ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/768 ,  H01L23/50 ,  H01L23/522 ,  G06F17/50 ,  H01L21/66 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

公开(公告)号：US20190067097A1

公开(公告)日：2019-02-28

申请号：US15686336

申请日：2017-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung Wang ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/768 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66 ,  G06F17/50

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

公开(公告)号：US10164034B2

公开(公告)日：2018-12-25

申请号：US15648269

申请日：2017-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jyun Huang ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator.

公开(公告)号：US10141296B2

公开(公告)日：2018-11-27

申请号：US15854358

申请日：2017-12-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Heng Hsieh ,  Tzung-Chi Lee ,  Yu-Jung Chang ,  Bao-Ru Young

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  G06F17/50

Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

公开(公告)号：US09773879B2

公开(公告)日：2017-09-26

申请号：US15157283

申请日：2016-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jyun Huang ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/02 ,  H01L29/417 ,  H01L21/311 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator.

公开(公告)号：US20170062559A1

公开(公告)日：2017-03-02

申请号：US15349100

申请日：2016-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。