公开(公告)号：US12057392B2

公开(公告)日：2024-08-06

申请号：US17648138

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-En Lee ,  Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang

IPC: H01L23/522 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L28/24

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

公开(公告)号：US11682579B2

公开(公告)日：2023-06-20

申请号：US17827480

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

IPC: H01L23/485 ,  H01L21/768 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/43

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/435 ,  H01L21/76895

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

公开(公告)号：US11532561B2

公开(公告)日：2022-12-20

申请号：US16984884

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/285 ,  H01L23/48

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US11227950B2

公开(公告)日：2022-01-18

申请号：US16572320

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/417 ,  H01L21/762 ,  H01L27/088

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US20210090943A1

公开(公告)日：2021-03-25

申请号：US17114174

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/43 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L23/485

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

公开(公告)号：US10923573B2

公开(公告)日：2021-02-16

申请号：US16572084

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Yu-Feng Yin ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao

IPC: H01L29/00 ,  H01L31/036 ,  H01L29/423 ,  H01L29/45 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

公开(公告)号：US10861740B2

公开(公告)日：2020-12-08

申请号：US16403921

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

IPC: H01L23/485 ,  H01L21/768 ,  H01L21/311 ,  H01L29/43 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

公开(公告)号：US10418453B2

公开(公告)日：2019-09-17

申请号：US15883238

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Yu-Feng Yin ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao

IPC: H01L29/00 ,  H01L31/036 ,  H01L29/423 ,  H01L29/45 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

公开(公告)号：US10283403B2

公开(公告)日：2019-05-07

申请号：US15722133

申请日：2017-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

IPC: H01L21/311 ,  H01L21/768 ,  H01L29/43 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L23/485

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

公开(公告)号：US09779984B1

公开(公告)日：2017-10-03

申请号：US15178229

申请日：2016-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/43 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/435

Abstract: A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process.