公开(公告)号：US20180026106A1

公开(公告)日：2018-01-25

申请号：US15215625

申请日：2016-07-21

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chia-Ling Yeh ,  Man-Ho Kwan ,  Kuei-Ming Chen ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai

IPC: H01L29/40 ,  H01L29/205 ,  H01L21/8252 ,  H01L29/66 ,  H01L27/06 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/408 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.

公开(公告)号：US11450749B2

公开(公告)日：2022-09-20

申请号：US16884292

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Chung Chang ,  Chun Lin Tsai ,  Ru-Yi Su ,  Wei Wang ,  Wei-Chen Yang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/868

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer.

公开(公告)号：US20220223699A1

公开(公告)日：2022-07-14

申请号：US17144671

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423

Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure.

公开(公告)号：US11349023B2

公开(公告)日：2022-05-31

申请号：US16589440

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Man-Ho Kwan ,  Fu-Wei Yao ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Ting-Fu Chang

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

公开(公告)号：US20220037518A1

公开(公告)日：2022-02-03

申请号：US17343153

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Wang ,  Wei-Chen Yang ,  Yao-Chung Chang ,  Ru-Yi Su ,  Yen-Ku Lin ,  Chuan-Wei Tsou ,  Chun Lin Tsai

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.

公开(公告)号：US11195945B2

公开(公告)日：2021-12-07

申请号：US16558518

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Cheng Lin ,  Chen-Bau Wu ,  Chun Lin Tsai ,  Haw-Yun Wu ,  Liang-Yu Su ,  Yun-Hsiang Wang

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/47 ,  H01L29/417

Abstract: In some embodiments, the present disclosure relates to a high voltage device that includes a substrate comprising a first semiconductor material. A channel layer that comprises a second semiconductor material is arranged over the substrate. An active layer that comprises a third semiconductor material is arranged over the channel layer. Over the active layer is a source contact spaced apart from a drain contact. A gate structure is arranged laterally between the source and drain contacts and over the active layer to define a high electron mobility transistor (HEMT) device. Between the gate structure and the source contact is a cap structure, which is coupled to the source contact and laterally spaced from the gate structure. The cap structure and a gate electrode of the gate structure comprise a same material.

公开(公告)号：US20200058647A1

公开(公告)日：2020-02-20

申请号：US16662496

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chiu-Hua Chung ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Tien Sheng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L27/07 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78 ,  H01L21/761

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

公开(公告)号：US10276657B2

公开(公告)日：2019-04-30

申请号：US15703084

申请日：2017-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Wei Yao ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Man-Ho Kwan

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L21/76 ,  H01L21/761

Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistore includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.

公开(公告)号：US20190006460A1

公开(公告)日：2019-01-03

申请号：US15694341

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Chiu ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Karthick Murukesan

IPC: H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to a high voltage resistor device that is able to receive high voltages using a small footprint, and an associated method of fabrication. In some embodiments, the high voltage resistor device has a substrate including a first region with a first doping type, and a drift region arranged within the substrate over the first region and having a second doping type. A body region having the first doping type laterally contacts the drift region. A drain region having the second doping type is arranged within the drift region, and an isolation structure is over the substrate between the drain region and the body region. A resistor structure is over the isolation structure and has a high-voltage terminal coupled to the drain region and a low-voltage terminal coupled to a gate structure over the isolation structure.

公开(公告)号：US20180226396A1

公开(公告)日：2018-08-09

申请号：US15942728

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0288 ,  H01L21/823475 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/405 ,  H01L29/4175 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.