公开(公告)号：US11855181B2

公开(公告)日：2023-12-26

申请号：US17676691

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao ,  Kuo-Liang Sung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L23/38 ,  H01L29/49 ,  H01L21/02 ,  H01L23/28 ,  H01L21/82 ,  H01L21/56

CPC classification number: H01L29/66545 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/56 ,  H01L21/82 ,  H01L23/28 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.

公开(公告)号：US11710779B2

公开(公告)日：2023-07-25

申请号：US17301482

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Yu-Wei Lu ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823807 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/785

Abstract: An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.

公开(公告)号：US20230058221A1

公开(公告)日：2023-02-23

申请号：US17406874

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/477

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

公开(公告)号：US20220359698A1

公开(公告)日：2022-11-10

申请号：US17870554

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Peng-Soon Lim ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28

Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

公开(公告)号：US11489056B2

公开(公告)日：2022-11-01

申请号：US16785919

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Peng-Soon Lim ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L27/092 ,  B82Y10/00

Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

公开(公告)号：US11267987B2

公开(公告)日：2022-03-08

申请号：US16805864

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Liao ,  An-Hsuan Lee ,  Shen-Nan Lee ,  Teng-Chun Tsai ,  Chen-Hao Wu ,  Huang-Lin Chao

IPC: C09G1/02 ,  H01L21/8238 ,  H01L21/321 ,  H01L21/306 ,  C09K3/14 ,  C09G1/06 ,  C09G1/00 ,  C09K13/06 ,  C09G1/04 ,  B24B1/00 ,  B24B37/04

Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.

公开(公告)号：US11183574B2

公开(公告)日：2021-11-23

申请号：US16690645

申请日：2019-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Ziwei Fang ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

公开(公告)号：US11038029B2

公开(公告)日：2021-06-15

申请号：US16277262

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Wen Tsau ,  Chun-I Wu ,  Ziwei Fang ,  Huang-Lin Chao ,  I-Ming Chang ,  Chung-Liang Cheng ,  Chih-Cheng Lin

IPC: H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/285 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

公开(公告)号：US20210130650A1

公开(公告)日：2021-05-06

申请号：US16805864

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Liao ,  An-Hsuan Lee ,  Shen-Nan Lee ,  Teng-Chun Tsai ,  Chen-Hao Wu ,  Huang-Lin Chao

IPC: C09G1/02 ,  H01L21/321 ,  H01L21/8238

Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.

公开(公告)号：US10714395B2

公开(公告)日：2020-07-14

申请号：US16277326

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chu-An Lee ,  Chen-Hao Wu ,  Peng-Chung Jangjian ,  Chun-Wen Hsiao ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC: H01L29/06 ,  H01L27/08 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.