公开(公告)号：US11424243B2

公开(公告)日：2022-08-23

申请号：US17121618

申请日：2020-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Chih-Liang Chen ,  Shi Ning Ju

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238

Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

公开(公告)号：US20210351279A1

公开(公告)日：2021-11-11

申请号：US17379208

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.

公开(公告)号：US11171053B2

公开(公告)日：2021-11-09

申请号：US16422559

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Lin-Yu Huang ,  Huan-Chieh Su ,  Sheng-Tsung Wang ,  Zhi-Chang Lin ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

公开(公告)号：US11139381B2

公开(公告)日：2021-10-05

申请号：US16655079

申请日：2019-10-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/165 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

公开(公告)号：US11069793B2

公开(公告)日：2021-07-20

申请号：US16446312

申请日：2019-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.

公开(公告)号：US10971605B2

公开(公告)日：2021-04-06

申请号：US16448704

申请日：2019-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/51 ,  H01L27/092

Abstract: A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.

公开(公告)号：US10861952B2

公开(公告)日：2020-12-08

申请号：US16206730

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

公开(公告)号：US20200381352A1

公开(公告)日：2020-12-03

申请号：US16427831

申请日：2019-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Ching ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L23/50 ,  H01L27/088 ,  H01L29/78

Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

公开(公告)号：US10818658B2

公开(公告)日：2020-10-27

申请号：US16045266

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ying-Keung Leung ,  Chi On Chui

IPC: H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/32 ,  H01L21/3105

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

公开(公告)号：US10763255B2

公开(公告)日：2020-09-01

申请号：US16103721

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L29/165 ,  H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/205

Abstract: A semiconductor device has a first fin, a second fin, an isolation structure between the first fin and the second fin, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure.