公开(公告)号：US20200221015A1

公开(公告)日：2020-07-09

申请号：US16822424

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming Chyi Liu ,  Tung-He Chou

IPC: H04N5/232 ,  G03B13/36 ,  H04N5/247 ,  G01S3/00 ,  G06K9/00 ,  G06K9/46 ,  G06K9/62 ,  H04N5/225 ,  H04N5/262

Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

公开(公告)号：US20200020856A1

公开(公告)日：2020-01-16

申请号：US16578304

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

公开(公告)号：US20200013953A1

公开(公告)日：2020-01-09

申请号：US16575725

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L49/02

Abstract: In some methods, a contact is formed over a substrate, and a bottom electrode layer is formed over the contact. A first dielectric layer is formed to cover a peripheral portion of the bottom electrode layer but not a central portion of the bottom electrode layer. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer includes a central dielectric region that contacts the central portion of the bottom electrode layer, and a peripheral dielectric region over the peripheral portion of the bottom electrode. A step dielectric region connects the central and peripheral dielectric regions. A top electrode layer is formed over the second dielectric layer. The top electrode layer includes a central top electrode region, a peripheral top electrode region, and a step top electrode region directly above the central dielectric region, the peripheral dielectric region, and the step dielectric region, respectively.

公开(公告)号：US10134945B1

公开(公告)日：2018-11-20

申请号：US15688200

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chen-Hua Yu ,  Chia-Shiung Tsai ,  Alexander Kalnitsky ,  Ru-Liang Lee ,  Eugene Chen

IPC: H01L21/30 ,  H01L21/46 ,  H01L33/00 ,  H01L21/762 ,  H01L21/18 ,  H01L21/285 ,  H01L21/8258

Abstract: A method for wafer to wafer bonding for III-V and CMOS wafers is provided. A silicon carrier wafer is provided having an epitaxial III-V semiconductor region and an oxide region disposed over the wafer top surface, the regions having substantially equal heights. A sidewall of the epitaxial III-V semiconductor region directly contacts a sidewall of the oxide region. A eutectic bonding layer is formed over a top surface of the epitaxial III-V semiconductor region and the oxide region for bonding to the CMOS wafer which contains semiconductor devices. The silicon carrier wafer is removed, and the CMOS wafer is singulated to form a plurality of three-dimensional integrated circuits, each including a CMOS substrate corresponding to a portion of the CMOS wafer and a III-V optical device corresponding to a portion of the III-V epitaxial semiconductor region.

公开(公告)号：US20180309055A1

公开(公告)日：2018-10-25

申请号：US16009327

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1691 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

公开(公告)号：US10003022B2

公开(公告)日：2018-06-19

申请号：US14196361

申请日：2014-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1691 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

公开(公告)号：US09711519B2

公开(公告)日：2017-07-18

申请号：US15170104

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L27/115 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11529 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11529 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates. A silicide contact pad is arranged over a top surface of the first memory cell gate. The silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate and the metal gate. A method of manufacturing the integrated circuit is also provided.

公开(公告)号：US20160111510A1

公开(公告)日：2016-04-21

申请号：US14980165

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a split gate flash memory cell is provided. A select gate is formed on a semiconductor substrate. A sacrificial spacer is formed laterally adjacent to the select gate and on a first side of the select gate. A charge trapping layer is formed lining upper surfaces of the select gate and the sacrificial spacer, and further lining a sidewall surface of the select gate on a second side of the select gate that is opposite the first side of the select gate. A memory gate is formed over the charge trapping layer and on the second side of the select gate. The sacrificial spacer is removed. The resulting semiconductor structure is also provided.

Abstract translation: 提供了一种制造分离栅闪存单元的方法。 选择栅极形成在半导体衬底上。 牺牲隔离物横向邻近选择栅极并在选择栅极的第一侧上形成。 在选择栅极和牺牲隔离物的上表面上形成电荷捕获层，并且进一步在选择栅极的与选择栅极的第一侧相对的第二侧上衬里选择栅极的侧壁表面。 存储栅极形成在电荷俘获层上和选择栅极的第二侧上。 去除牺牲隔离物。 还提供所得的半导体结构。

公开(公告)号：US20160013198A1

公开(公告)日：2016-01-14

申请号：US14330140

申请日：2014-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28008 ,  H01L21/28273 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions. A silicide contact pad is arranged over a top surface of the memory cell gate. The top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions. A method of manufacturing the integrated circuit is also provided.

Abstract translation: 提供了一种用于嵌入式闪存设备的集成电路。 半导体衬底包括存储区域和与存储区域相邻的逻辑区域。 逻辑器件布置在逻辑区域上，并且包括通过具有超过3.9的介电常数的材料与半导体衬底分离的金属栅极。 闪存单元设备布置在存储器区域的上方。 闪存单元器件包括通过相应的电介质区域在相对侧上电绝缘的存储单元栅极。 硅化物接触焊盘设置在存储单元栅极的顶表面上方。 存储单元栅极的顶表面和硅化物接触焊盘的顶表面相对于金属栅极的顶表面和电介质区域的顶表面凹陷。 还提供了一种制造集成电路的方法。

公开(公告)号：US20150311435A1

公开(公告)日：2015-10-29

申请号：US14261526

申请日：2014-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L28/40 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16

Abstract: An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents.

Abstract translation: 集成电路装置包括电阻随机存取存储器（RRAM）单元或具有电介质层，顶部导电层和底部导电层的MIM电容器单元。 电介质层包括与电介质层的边缘相邻的周边区域和由周边区域包围的中心区域。 顶部导电层邻接并位于介电层上方。 底部导电层邻接并且在中心区域的介电层下方，但不与电介质层邻接电池的外围区域。 可以通过底部导电层和专门在周边区域中的电介质层之间的附加电介质层或通过切割比周边区域短的底部电极层来防止基台。 电介质层边缘的损伤或污染不会导致漏电流。