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    Semiconductor device and method
    33.
    发明授权
    Semiconductor device and method 有权

    公开(公告)号：US12266687B2

    公开(公告)日：2025-04-01

    申请号：US17650712

    申请日：2022-02-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Yu Lin ,  Ming-Hua Yu ,  Yee-Chia Yeo

    IPC: H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

    Abstract: A method includes forming a fin protruding from a substrate; forming an isolation region surrounding the fin; forming a gate structure extending over the fin and the isolation region; etching the fin adjacent the gate structure to form a recess; forming a source/drain region in the recess, including performing a first epitaxial process to grow a first semiconductor material in the recess, wherein the first epitaxial process preferentially forms facet planes of a first crystalline orientation; and performing a second epitaxial process to grow a second semiconductor material on the first semiconductor material, wherein the second epitaxial process preferentially forms facet planes of a second crystalline orientation, wherein a top surface of the second semiconductor material is above a top surface of the fin; and forming a source/drain contact on the source/drain region.

    Confined Source/Drain Epitaxy Regions and Method Forming Same
    36.
    发明公开
    Confined Source/Drain Epitaxy Regions and Method Forming Same 审中-公开

    公开(公告)号：US20240204044A1

    公开(公告)日：2024-06-20

    申请号：US18589160

    申请日：2024-02-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jeng-Wei Yu ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Li-Wei Chou ,  Ming-Hua Yu

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78651

    Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.

    Transistors with Stacked Semiconductor Layers as Channels
    40.
    发明申请
    Transistors with Stacked Semiconductor Layers as Channels 有权

    公开(公告)号：US20220181440A1

    公开(公告)日：2022-06-09

    申请号：US17651858

    申请日：2022-02-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsi Yang ,  Ming-Hua Yu ,  Jeng-Wei Yu

    IPC: H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

    Abstract: A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.

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