公开(公告)号：US20210013338A1

公开(公告)日：2021-01-14

申请号：US17034176

申请日：2020-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Jung-Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

公开(公告)号：US10312149B1

公开(公告)日：2019-06-04

申请号：US15810831

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Yi-Cheng Chao ,  Chai-Wei Chang ,  Po-Chi Wu ,  Jung-Jui Li

IPC: H01L21/8234 ,  H01L29/66

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate, and the substrate includes a first region and a second region. The FinFET structure includes a first plurality of fin structures formed on the first region and a second plurality of fin structures formed on the second region. A density of the first plurality of fin structures is greater than a density of the second plurality of fin structures. The FinFET structure also includes a plurality of protruding structures between two adjacent second plurality of fin structures in the second region and an isolation structure formed on the substrate. The isolation structure has a gap height between the first plurality of fin structures and the second plurality of fin structures.

公开(公告)号：US09991256B2

公开(公告)日：2018-06-05

申请号：US14968468

申请日：2015-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

公开(公告)号：US09799565B2

公开(公告)日：2017-10-24

申请号：US14625291

申请日：2015-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chai-Wei Chang ,  Po-Chi Wu ,  Wen-Han Fang

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/51 ,  H01L21/3105

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.