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    HYBRID BOND PAD STRUCTURE
    31.
    发明申请
    HYBRID BOND PAD STRUCTURE 有权

    公开(公告)号：US20210288029A1

    公开(公告)日：2021-09-16

    申请号：US17333120

    申请日：2021-05-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

    IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L27/146 ,  H01L23/00

    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.

    Structure improving reliability of top electrode contact for resistance switching RAM having cells of varying height
    32.
    发明授权
    Structure improving reliability of top electrode contact for resistance switching RAM having cells of varying height 有权

    公开(公告)号：US11121315B2

    公开(公告)日：2021-09-14

    申请号：US16733378

    申请日：2020-01-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Tai Hsiao ,  Sheng-Chau Chen ,  Hsun-Chung Kuang

    IPC: H01L45/00

    Abstract: The problem of forming top electrode vias that provide consistent results in devices that include resistance switching RAM cells of varying heights is solved using a dielectric composite that fills areas between resistance switching RAM cells and varies in height to align with the tops of both the taller and the shorter resistance switching RAM cells. An etch stop layer may be formed over the dielectric composite providing an equal thickness of etch-resistant dielectric over both taller and shorter resistance switching RAM cells. The dielectric composite causes the etch stop layer to extend laterally away from the resistance switching RAM cells to maintain separation between the via openings and the resistance switching RAM cell sides even when the openings are misaligned.

    TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING
    34.
    发明申请
    TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING 有权

    公开(公告)号：US20210134694A1

    公开(公告)日：2021-05-06

    申请号：US16785866

    申请日：2020-02-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu

    IPC: H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

    DEEP TRENCH ISOLATION SHRINKAGE METHOD FOR ENHANCED DEVICE PERFORMANCE
    36.
    发明申请
    DEEP TRENCH ISOLATION SHRINKAGE METHOD FOR ENHANCED DEVICE PERFORMANCE 审中-公开

    公开(公告)号：US20190259804A1

    公开(公告)日：2019-08-22

    申请号：US16405102

    申请日：2019-05-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

    IPC: H01L27/146 ,  H01L21/8238 ,  H01L33/20

    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

    Deep trench isolation shrinkage method for enhanced device performance
    37.
    发明授权
    Deep trench isolation shrinkage method for enhanced device performance 有权

    公开(公告)号：US10325956B2

    公开(公告)日：2019-06-18

    申请号：US15591722

    申请日：2017-05-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

    IPC: H01L33/20 ,  H01L27/146 ,  H01L21/8238

    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

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