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    Forming Isolation Regions for Separating Fins and Gate Stacks
    31.
    发明申请
    Forming Isolation Regions for Separating Fins and Gate Stacks 有权

    公开(公告)号：US20220359299A1

    公开(公告)日：2022-11-10

    申请号：US17813850

    申请日：2022-07-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Jr-Hung Li ,  Tze-Liang Lee ,  Chi On Chui

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088

    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

    Isolation Features and Methods of Fabricating the Same
    33.
    发明申请
    Isolation Features and Methods of Fabricating the Same 有权

    公开(公告)号：US20210273049A1

    公开(公告)日：2021-09-02

    申请号：US17322087

    申请日：2021-05-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： I-Wen Wu ,  Fu-Kai Yang ,  Chen-Ming B. Lee ,  Mei-Yun Wang ,  Jr-Hung Li ,  Bo-Cyuan Lu

    IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762 ,  H01L29/78

    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

    Low-K gate spacer and formation thereof
    36.
    发明授权
    Low-K gate spacer and formation thereof 有权

    公开(公告)号：US10510612B2

    公开(公告)日：2019-12-17

    申请号：US16203814

    申请日：2018-11-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417

    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

    Transistor Contacts and Methods of Forming the Same
    40.
    发明公开
    Transistor Contacts and Methods of Forming the Same 审中-公开

    公开(公告)号：US20240021476A1

    公开(公告)日：2024-01-18

    申请号：US18151181

    申请日：2023-01-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chun-Kai Chen

    IPC: H01L21/768 ,  H01L29/66

    CPC classification number: H01L21/76897 ,  H01L29/6656 ,  H01L21/76813 ,  H01L29/66545

    Abstract: In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.

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