公开(公告)号：US20210098365A1

公开(公告)日：2021-04-01

申请号：US16805834

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Liang-Yin Chen ,  Su-Hao Liu ,  Tze-Liang Lee ,  Meng-Han Chou ,  Kuo-Ju Chen ,  Huicheng Chang ,  Tsai-Jung Ho ,  Tzu-Yang Ho

IPC: H01L23/522 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

公开(公告)号：US10854729B2

公开(公告)日：2020-12-01

申请号：US16578360

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/265

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

公开(公告)号：US20200295131A1

公开(公告)日：2020-09-17

申请号：US16889401

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chun HUANG ,  Bor Chiuan Hsieh ,  Pei-Ren Jeng ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

公开(公告)号：US20180350906A1

公开(公告)日：2018-12-06

申请号：US16043244

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chun Huang ,  Bor Chiuan Hsieh ,  Pei-Ren Jeng ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/02

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

公开(公告)号：US09991364B2

公开(公告)日：2018-06-05

申请号：US15612137

申请日：2017-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/737 ,  H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L21/265 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7378 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/7848

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

公开(公告)号：US20170271478A1

公开(公告)日：2017-09-21

申请号：US15612137

申请日：2017-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7378 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/7848

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

公开(公告)号：US09281196B2

公开(公告)日：2016-03-08

申请号：US14175194

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/66537 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract translation: 本公开涉及一种形成晶体管器件的方法。 在该方法中，第一和第二阱区形成在半导体衬底内。 第一和第二阱区域分别具有彼此不同的第一和第二蚀刻速率。 将掺杂剂选择性地注入第一阱区以改变第一蚀刻速率以使第一蚀刻速率基本上等于第二蚀刻速率。 蚀刻第一选择性注入的阱区和第二阱区以形成具有相等凹槽深度的沟槽。 进行外延生长工艺以在通道凹槽内形成一个或多个外延层。

公开(公告)号：US20150349065A1

公开(公告)日：2015-12-03

申请号：US14288587

申请日：2014-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/36 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L27/092

Abstract: The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel regions. An epitaxially grown diffusion barrier layer separates the epitaxial grown channel regions from underlying deep n-wells and p-wells. The epitaxial source/drain regions allow for a low thermal budget that in combination with the diffusion barrier layer allows the deep n-wells and p-wells to be heavily doped while preserving high purity in the channel layers.

Abstract translation: 本公开提供了包括n沟道和p沟道MOSFET的集成电路器件。 MOSFET包括外延生长的升高的源极/漏极区域和外延生长的沟道区域。 外延生长的扩散阻挡层将外延生长的沟道区域从下面的深n阱和p阱分离。 外延源极/漏极区域允许低热量预算，与扩散阻挡层组合允许深n阱和p阱重掺杂，同时在通道层中保持高纯度。

公开(公告)号：US20150187927A1

公开(公告)日：2015-07-02

申请号：US14175194

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract translation: 本公开涉及一种形成晶体管器件的方法。 在该方法中，第一和第二阱区形成在半导体衬底内。 第一和第二阱区域分别具有彼此不同的第一和第二蚀刻速率。 将掺杂剂选择性地注入第一阱区以改变第一蚀刻速率以使第一蚀刻速率基本上等于第二蚀刻速率。 蚀刻第一选择性注入的阱区和第二阱区以形成具有相等凹槽深度的沟槽。 进行外延生长工艺以在通道凹槽内形成一个或多个外延层。

公开(公告)号：US20250151317A1

公开(公告)日：2025-05-08

申请号：US19015324

申请日：2025-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Chi-Hao Chang ,  Jr-Hung Li

IPC: H10D30/62 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.