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    PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING
    31.
    发明申请
    PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING 审中-公开
    多彩图案的预色彩方法

    公开(公告)号：US20140068531A1

    公开(公告)日：2014-03-06

    申请号：US14076566

    申请日：2013-11-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Huei Chen ,  Wei Min Chan ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5068 ,  G06F2217/12

    Abstract: Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.

    Abstract translation: 一些实施例涉及用于在集成芯片布局内预先着色数据的方法，以避免在多次图案化光刻期间由掩模未对准而产生的重叠误差。 该方法可以通过生成包含具有多个IC形状的集成芯片布局的图形IC布局文件来执行。 图形IC布局文件中的IC形状在分解过程中会分配一种颜色。 IC形状进一步预先着色，以故意将预色数据分配给相同的掩码。 在掩模建立过程中，与预先着色的IC形状相关联的数据将自动发送到相同的掩码，而不管分配给形状的颜色如何。 因此，预先着色的形状不是基于分解而分配给掩蔽的，而是基于预着色。 通过预先着色将IC形状分配给相同的掩模，可以减少重叠错误。

    Memory cell
    33.
    发明授权
    Memory cell 有权

    公开(公告)号：US11176997B2

    公开(公告)日：2021-11-16

    申请号：US17186539

    申请日：2021-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

    IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    Memory with write assist circuit
    38.
    发明授权
    Memory with write assist circuit 有权

    公开(公告)号：US09741429B1

    公开(公告)日：2017-08-22

    申请号：US15099706

    申请日：2016-04-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Huei Chen ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

    IPC: G11C11/00 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/413

    Abstract: A memory device with an array of memory cells, a write driver circuit, and a write assist circuit is disclosed. The write driver circuit and the write assist circuit can be located opposite to one another relative to the array of memory cells. The write assist circuit can compensate for a parasitic element in bitlines by transferring write voltages to addressed memory cells located in a portion of a memory array opposite to the write driver circuit. The parasitic element can be, for example, a bitline path resistance that causes a voltage differential between a voltage at the output of the write driver circuit and another voltage at a bitline location associated with the addressed memory cell. The write assist circuit can compensate for the voltage differential at the bitline location associated with the addressed memory cell; thus improving the performance of memory write operations.

    Memory device with stable writing and/or reading operation
    39.
    发明授权
    Memory device with stable writing and/or reading operation 有权
    具有稳定写入和/或读取操作的存储器件

    公开(公告)号：US09496026B1

    公开(公告)日：2016-11-15

    申请号：US14700135

    申请日：2015-04-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Mohammed Hasan Taufique ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Yen-Huei Chen

    IPC: G11C11/00 ,  G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  G11C7/22

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C7/22 ,  G11C11/412

    Abstract: A memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.

    Abstract translation: 存储器件包括第一反相器，与第一反相器交叉耦合的第二反相器，存取单元和切换单元。 访问单元被配置为对第一反相器的输出进行放电，并根据由第一字线和第二字线提供的信号对第二反相器的输出进行充电。 开关单元被配置为根据由第一字线提供的信号来断开来自第一逆变器和第二逆变器的电力。

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