公开(公告)号：US08674481B2

公开(公告)日：2014-03-18

申请号：US12261121

申请日：2008-10-30

申请人： Steven R. Droes ,  Yutaka Takafuji

发明人： Steven R. Droes ,  Yutaka Takafuji

IPC分类号： H01L21/30

CPC分类号： H01L21/3221 ,  H01L21/26506 ,  H01L21/76254 ,  H01L27/1266 ,  H01L29/66772 ,  H01L29/78603

摘要： A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing.

摘要翻译： 提供氢（H）剥离吸气方法，用于将制造的电路连接到接收器基板。 该方法包括：提供Si衬底; 在电路源极/漏极（S / D）区域上形成覆盖衬底的Si有源层; 将P掺杂剂注入到S / D区域中; 形成S / D区域下游的吸气区域; 在Si衬底中注入H，在Si衬底中形成与吸杂区一样深的切割面（峰值浓度（Rp）H层）; 将电路接合到接收器基板; 沿着切割面切割Si衬底; 并且作为后键合退火的结果，在吸杂区域中将S / D区域下面的注入的H与p掺杂剂结合。

公开(公告)号：US08421076B2

公开(公告)日：2013-04-16

申请号：US12674560

申请日：2008-09-08

申请人： Michiko Takei ,  Shin Matsumoto ,  Kazuhide Tomiyasu ,  Yasumori Fukushima ,  Yutaka Takafuji

发明人： Michiko Takei ,  Shin Matsumoto ,  Kazuhide Tomiyasu ,  Yasumori Fukushima ,  Yutaka Takafuji

IPC分类号： H01L29/72

CPC分类号： H01L27/1266 ,  H01L21/02076 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/78603 ,  Y10T428/24355

摘要： The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.

摘要翻译： 本发明旨在提供一种由绝缘材料制成的玻璃基板（20），其可以通过将单晶硅膜（50）或包括半导体器件的基板转移到表面上而构成半导体装置（10） 24），作为表面（24）的一部分的转印面（26），能够设置在转印面（26）上的单晶硅膜（50），转印面（26）具有 算术平均粗糙度不大于0.4nm。

公开(公告)号：US08101502B2

公开(公告)日：2012-01-24

申请号：US12600813

申请日：2008-04-01

申请人： Yasumori Fukushima ,  Yutaka Takafuji ,  Kazuhide Tomiyasu ,  Michiko Takei ,  Steven Droes

发明人： Yasumori Fukushima ,  Yutaka Takafuji ,  Kazuhide Tomiyasu ,  Michiko Takei ,  Steven Droes

IPC分类号： H01L21/22

CPC分类号： H01L27/12 ,  H01L21/2007 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/76254 ,  H01L21/84 ,  H01L29/78636 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/00

摘要： A device portion forming step includes an assisting layer forming step of forming a planarization assisting layer, which covers a plurality of conductive films, over a first planarizing layer before forming a second planarizing layer. In the assisting layer forming step, the planarization assisting layer is formed so that a height of the planarization assisting layer from a surface of the first planarizing layer located on a side opposite to the substrate layer becomes equal between at least a part of a region where the conductive films are formed, and at least a part of a region where no conductive film is formed.

摘要翻译： 器件部分形成步骤包括辅助层形成步骤，在形成第二平坦化层之前，在第一平坦化层上形成覆盖多个导电膜的平坦化辅助层。 在辅助层形成步骤中，形成平坦化辅助层，使得平坦化辅助层从位于与衬底层相反的一侧的第一平坦化层的表面的高度在至少一部分区域之间变得相等， 形成导电膜，并且形成不形成导电膜的区域的至少一部分。

公开(公告)号：US20110309467A1

公开(公告)日：2011-12-22

申请号：US13141332

申请日：2009-11-25

申请人： Shin Matsumoto ,  Yutaka Takafuji ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Kenshi Tada

发明人： Shin Matsumoto ,  Yutaka Takafuji ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Kenshi Tada

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L27/1266

摘要： Disclosed is a semiconductor device including a substrate for bonding (10a), and a semiconductor element part (25aa) which is bonded to the substrate (10a), and in which an element pattern (T) is formed, wherein in a bonded interface between the substrate (10a) and the semiconductor element part (25aa), recessed portions (23a) are formed in at least one of the substrate (10a) and the semiconductor element part (25aa).

摘要翻译： 公开了一种包括用于接合的基板（10a）的半导体器件和接合到基板（10a）的半导体元件部分（25aa），并且其中形成有元件图案（T），其中在 在基板（10a）和半导体元件部（25aa）中的至少一个上形成有基板（10a）和半导体元件部（25a），凹部（23a）。

公开(公告)号：US07923310B2

公开(公告)日：2011-04-12

申请号：US11779220

申请日：2007-07-17

申请人： Mark A. Crowder ,  Yutaka Takafuji

发明人： Mark A. Crowder ,  Yutaka Takafuji

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6675 ,  H01L29/78621 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/055 ,  Y10S438/962 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/938

摘要： A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure. The source/drain (S/D) regions in end sections of the CS nanostructure flanking are doped.

摘要翻译： 提供了用于核 - 壳 - 壳（CSS）纳米线晶体管（NWT）的制造方法。 该方法提供了具有半导体芯，绝缘体壳和导电壳的圆柱形CSS纳米结构。 CSS纳米结构具有覆盖衬底表面的较低的半圆柱体。 第一绝缘膜被保形地沉积在CSS纳米结构和各向异性等离子体蚀刻上。 在纳米结构较低的半圆柱体附近形成绝缘折痕桁条。 导电膜被共形沉积，并且选择的区域是各向异性等离子体蚀刻，在CSS纳米结构的中心部分形成覆盖栅电极的导电膜栅极带。 各向同性蚀刻除去邻近CSS纳米结构的中心部分的绝缘折返桁条，并且执行覆盖S / D区域的导电壳体的各向同性蚀刻。 屏幕氧化物层沉积在CSS纳米结构上。 在CS纳米结构侧面的末端部分的源极/漏极（S / D）区域被掺杂。

公开(公告)号：US20110058126A1

公开(公告)日：2011-03-10

申请号：US12867725

申请日：2009-02-10

申请人： Yasunobu Okada ,  Akihide Shibata ,  Yoshiharu Nakajima ,  Hiroshi Iwata ,  Ai Naitou ,  Yutaka Takafuji ,  Tetsu Negishi

发明人： Yasunobu Okada ,  Akihide Shibata ,  Yoshiharu Nakajima ,  Hiroshi Iwata ,  Ai Naitou ,  Yutaka Takafuji ,  Tetsu Negishi

IPC分类号： G02F1/1333 ,  H01L29/41 ,  H01L21/44

CPC分类号： H01L27/283 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/78696 ,  H01L51/0012 ,  H01L51/0545

摘要： With reference to a direction perpendicular to a direction of forming electrodes to which a voltage can be applied, fine structures are each arranged within ±5 degrees at a substantially even interval, and a semiconductor element is formed by using the fine structures. On an insulating substrate, at least two electrodes are arranged at a predetermined interval, and there are formed one or more fine structure arranging regions, each of which is formed by a unit of the two electrodes. A semiconductor element electrode is made in contact with the plurality of the fine structures, each having two ends in contact with the two electrodes and a length in a longitudinal direction of a nano order to a micron order, and arranged within ±5 degrees with reference to the direction perpendicular to the direction of forming the electrodes.

摘要翻译： 关于与形成可施加电压的电极的方向垂直的方向，精细结构以基本上均匀的间隔布置在±5度内，并且通过使用精细结构形成半导体元件。 在绝缘基板上，至少两个电极以预定间隔布置，并且形成一个或多个精细结构布置区域，每个电极由两个电极的单元形成。 半导体元件电极与多个精细结构接触，每个微结构具有与两个电极接触的两个端部，并且在纵向方向上的长度为纳米级至微米级，并且以参考方式布置在±5度内 到垂直于形成电极的方向的方向。

公开(公告)号：US20100295105A1

公开(公告)日：2010-11-25

申请号：US12746323

申请日：2008-09-25

申请人： Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Yutaka Takafuji ,  Kenshi Tada ,  Michiko Takei

发明人： Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Yutaka Takafuji ,  Kenshi Tada ,  Michiko Takei

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L29/73 ,  H01L29/861 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.

摘要翻译： 一种制造半导体器件的方法包括：元件部分形成步骤，在基底层上形成元件部分; 在所述基底层中形成剥离层的剥离层形成工序; 键合步骤，将具有元件部分的基底层粘合到基底上; 以及分离步骤，通过加热结合到基板的基底层，沿着剥离层在深度方向上分离和去除基底层的一部分。 该方法还包括在分离步骤之后的离子注入步骤，用于在基底层中离子注入p型杂质元素，以调整元件的p型区域的杂质浓度。

公开(公告)号：US20100270618A1

公开(公告)日：2010-10-28

申请号：US12741852

申请日：2008-10-14

申请人： Michiko Takei ,  Yutaka Takafuji ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Steven Roy Droes

发明人： Michiko Takei ,  Yutaka Takafuji ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Steven Roy Droes

IPC分类号： H01L29/786 ,  H01L21/762 ,  H01L23/48

CPC分类号： H01L27/1266 ,  H01L21/31053 ,  H01L21/76819 ,  H01L27/1214 ,  H01L29/66772

摘要： The present invention provides a production method of a semiconductor device, capable of improving surface flatness of a semiconductor chip formed on a semiconductor substrate and thereby suppressing a variation in electrical characteristics of the semiconductor chip transferred onto a substrate with an insulating surface, and further capable of improving production yield. The present invention provides a production method of a semiconductor device including a semiconductor chip on a substrate with an insulating surface, the semiconductor chip having a conductive pattern film, the production method including the following successive steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer. The present invention is also a semiconductor device produced by the production method.

摘要翻译： 本发明提供一种半导体器件的制造方法，其能够提高形成在半导体基板上的半导体芯片的表面平坦性，从而抑制转印到具有绝缘表面的基板上的半导体芯片的电特性的变化， 提高产量。 本发明提供一种半导体器件的制造方法，该半导体器件在具有绝缘表面的衬底上具有半导体芯片，该半导体芯片具有导电图案膜，该制造方法包括以下连续步骤：在半导体上形成第一绝缘膜 并且在形成在半导体衬底上的导电图案膜上，并且通过图案化在导电图案膜布置的区域中减小第一绝缘膜的厚度; 形成第二绝缘膜并抛光第二绝缘膜，从而形成平坦化膜; 通过平坦化的膜将用于裂解的物质注入到半导体衬底中，从而形成裂解层; 将半导体芯片转印到具有绝缘表面的基板上，使得与半导体基板相对的一侧的芯片表面附着在其上; 并将半导体衬底与解理层分离。 本发明也是通过该制造方法制造的半导体装置。

公开(公告)号：US20100252885A1

公开(公告)日：2010-10-07

申请号：US12742463

申请日：2008-09-19

申请人： Yasumori Fukushima ,  Yutaka Takafuji ,  Kenshi Tada

发明人： Yasumori Fukushima ,  Yutaka Takafuji ,  Kenshi Tada

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L27/12 ,  H01L29/78603 ,  H01L29/78621

摘要： A semiconductor device (10) is formed by bonding a semiconductor substrate (1) including a CMOS transistor (3) to a glass substrate (2). The semiconductor substrate (1) is formed by partial separation at a separation layer. A P-type high concentration impurity region (39n) is formed in electric connection with a channel region (35n) of an NMOS transistor (3n) so that an electric potential of the channel region (35n) is fixed. The P-type high concentration impurity region (39n) has the same P conductive type as that of the channel region (35n) and also has a concentration higher than that of the channel region (35n). An N-type high concentration impurity region (39p) is formed in electric connection with a channel region (35p) of a PMOS transistor (3p) so that an electric potential of the channel region (35p) is fixed. The N-type high concentration impurity region (39p) has the same N conductive type as that of the channel region (35p) and also has a concentration higher than that of the channel region (35p). This makes it possible to provide a semiconductor device whose performance can be enhanced by restraint on variation in a characteristic of a thin film transistor and a display device including the semiconductor device.

摘要翻译： 半导体器件（10）通过将包括CMOS晶体管（3）的半导体衬底（1）结合到玻璃衬底（2）而形成。 半导体衬底（1）通过在分离层处的部分分离而形成。 形成与NMOS晶体管（3n）的沟道区（35n）电连接的P型高浓度杂质区（39n），使得沟道区（35n）的电位固定。 P型高浓度杂质区域（39n）具有与沟道区域（35n）相同的P导电型，并且其浓度高于沟道区域（35n）的浓度。 形成与PMOS晶体管（3p）的沟道区（35p）电连接的N型高浓度杂质区（39p），使得沟道区（35p）的电位固定。 N型高浓度杂质区（39p）具有与沟道区（35p）相同的N导电型，其浓度高于沟道区（35p）。 这使得可以提供一种通过限制薄膜晶体管的特性变化和包括半导体器件的显示装置来提高其性能的半导体器件。

公开(公告)号：US20100252813A1

公开(公告)日：2010-10-07

申请号：US11779220

申请日：2007-07-17

申请人： Mark A. Crowder ,  Yutaka Takafuji

发明人： Mark A. Crowder ,  Yutaka Takafuji

IPC分类号： H01L29/775 ,  H01L21/336

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6675 ,  H01L29/78621 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/055 ,  Y10S438/962 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/938

摘要： A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure. The source/drain (S/D) regions in end sections of the CS nanostructure flanking are doped.

摘要翻译： 提供了用于核 - 壳 - 壳（CSS）纳米线晶体管（NWT）的制造方法。 该方法提供了具有半导体芯，绝缘体壳和导电壳的圆柱形CSS纳米结构。 CSS纳米结构具有覆盖衬底表面的较低的半圆柱体。 第一绝缘膜被保形地沉积在CSS纳米结构和各向异性等离子体蚀刻上。 在纳米结构较低的半圆柱体附近形成绝缘折痕桁条。 导电膜被共形沉积，并且选择的区域是各向异性等离子体蚀刻，在CSS纳米结构的中心部分形成覆盖栅电极的导电膜栅极带。 各向同性蚀刻除去邻近CSS纳米结构的中心部分的绝缘折返桁条，并且执行覆盖S / D区域的导电壳体的各向同性蚀刻。 屏幕氧化物层沉积在CSS纳米结构上。 在CS纳米结构侧面的末端部分的源极/漏极（S / D）区域被掺杂。