摘要:
Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.
摘要:
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要:
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要:
Linear integrated circuit capacitors having greater capacitance per unit area by using lateral flux. One embodiment comprises a two metal layer capacitor wherein each metal layer is comprised of two capacitor conductive components. The capacitor conductive components are cross-coupled so that the total capacitance is the sum of the vertical flux between the metal layers, and the lateral flux along the edges between the two capacitor conductive components in each of the metal layers. The lateral flux between the capacitor conductive components in a single metal layer increases the capacitance per unit area and decreases the bottom-plate parasitic capacitance. Increasing the length of the common edge formed by capacitor conductive components in a metal layer increases the capacitance per unit area. In one lateral flux capacitor, each metal layer is comprised of a plurality of rows, alternate rows are coupled together such that lateral flux is generated between each of the rows. The rows are also cross-coupled with rows in adjacent metal layers to provide vertical flux. Fractal shapes can be used to maximize the length of the perimeter of adjacent capacitor conductive components in a single metal layer. The Koch Islands and Minkowski Sausage families of fractals are particularly well suited for generating capacitor conductive component perimeter shapes. These fractals are generated by selecting an initiator shape and repeatedly applying a generator. The fractal shapes are generated by a computer program based upon user input parameters.
摘要:
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要:
A distributed electrostatic discharge (ESD) protection circuit for high frequency integrated circuits. A transmission line from an integrated circuit (IC) pad or package pin couples a plurality of ESD elements. The ESD elements, such as diodes, are distributed along the transmission line and coupled from the transmission line to ground or a power supply. The effective impedance of the transmission line and ESD elements is defined to match the impedance of an external line. Distributed ESD protection circuits provide a high frequency signal path that can be used well into the GHz frequency range and also provide effective ESD protection.
摘要:
A temperature sensor includes a bandgap reference circuit for providing a temperature-independent reference voltage, a biasing circuit that mirrors a current in the bandgap reference circuit for providing a temperature-dependent biasing voltage, and an amplifier responsive to the reference voltage and the biasing voltage for providing a temperature-dependent output voltage. Preferably, the temperature sensor is integral with a microprocessor and implemented in CMOS technology. The temperature sensor can be used, for instance, to reduce the clock speed of the microprocessor when the microprocessor temperature exceeds a predetermined temperature, or to store temperature-indicating data in non-volatile memory of the microprocessor to provide a thermal history of the microprocessor.
摘要:
A high gain, low voltage differential amplifier exhibiting extremely low common mode sensitivities includes a load element exhibiting a high differential resistance, but a low common mode resistance. The load element contains a positive differential load resistance and a negative differential load resistance, which offsets the positive differential load resistance. The output common mode level of the differential amplifier is one p-channel source to gate voltage drop below the power supply voltage prohibiting the common mode output voltage from drifting far from an active level. The differential amplifier also has application for use in a differential charge pump circuit. The high differential impedance of the differential amplifier allows the attainment of extremely small leakage, while a low common-mode impedance results in simplified biasing.
摘要:
An electronic component test device capable of testing electronic components in a plurality of test configurations. The device includes a probe head for providing a plurality of probe contact structures to an electronic component to be tested. The device includes an interconnect board coupled to the probe head. The interconnect board includes a plurality of conductive terminals, each of a first subset of the plurality of conductive terminals is coupled to one of a group of electrical signal lines for coupling to different types of external signals. The interconnect board includes a plurality of conductive lines. Each conductive line is coupled between a corresponding one of a plurality of conductive terminals in a second subset of the plurality of conductive terminals and a terminal for coupling to one of the plurality of probe contact structures. Each conductive terminal of the second subset is couplable by an interconnector of a plurality of interconnectors to a conductive terminal of multiple conductive terminals of the first subset based on a test configuration of the device.
摘要:
A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.