公开(公告)号：US6087700A

公开(公告)日：2000-07-11

申请号：US21729

申请日：1998-02-11

申请人： Pierre C. Fazan ,  Hiang C. Chan

发明人： Pierre C. Fazan ,  Hiang C. Chan

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/76

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061

摘要： A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

摘要翻译： 制造具有硅化钛阻挡层的栅极的方法包括形成栅氧化层的步骤。 栅极氧化物可以使用标准LOCOS工艺形成。 掺杂多晶硅层沉积在栅极氧化物层上。 相对于掺杂多晶硅层以预定的关系形成硅化钛层，即其可沉积在多晶硅的顶部或形成在多晶硅层的顶表面中。 在硅化钛层的顶部上沉积一层硅化钨。 蚀刻栅极氧化物，掺杂多晶硅，硅化钛和硅化钨的层以形成栅极。 还公开了如此制造的栅极。

公开(公告)号：US6030847A

公开(公告)日：2000-02-29

申请号：US572392

申请日：1995-12-14

申请人： Pierre C. Fazan ,  Viju K. Mathews

发明人： Pierre C. Fazan ,  Viju K. Mathews

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01G7/06

CPC分类号： H01L27/11502 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/55 ,  H01L28/75

摘要： The invention is a storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layers is formed in the recess and the top layer. The process continued with a formation of an oxidation resistant conductive layer and the deposition of a further oxide layer to fill remaining portions of the recess. The oxidation resistant conductive layer is planarized to expose the oxide or oxide/nitride layer and the oxide layers are then etched to expose the top surface and vertical portions of the oxidation resistant conductive layer.Next a dielectric layer having a high dielectric constant is formed to overlie the storage node electrode and a cell plate electrode is fabricated to overlie the dielectric layer.

摘要翻译： 本发明是具有存储节点电极的存储单元电容器，该存储节点电极包括介于导电插塞和抗氧化层之间的阻挡层。 厚的绝缘层在具有高介电常数的介电层的沉积和退火期间保护阻挡层的侧壁。 该方法包括在诸如氧化物或氧化物/氮化物的绝缘材料的厚层中形成导电插塞。 导电插塞从厚绝缘层的平坦化顶表面凹陷。 阻挡层形成在凹部和顶层中。 该过程继续形成抗氧化导电层和沉积另外的氧化物层以填充凹部的剩余部分。 将抗氧化导电层平坦化以暴露氧化物或氧化物/氮化物层，然后蚀刻氧化物层以暴露抗氧化导电层的顶部表面和垂直部分。 接下来，形成具有高介电常数的介电层以覆盖存储节点电极，并且制造单元板电极以覆盖介电层。

公开(公告)号：US6017789A

公开(公告)日：2000-01-25

申请号：US881561

申请日：1997-06-24

申请人： Gurtej S. Sandhu ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Pierre C. Fazan

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/56 ,  H01L28/40

摘要： A method of forming a dielectric layer includes, a) chemical vapor depositing a dielectric layer of Ta.sub.2 O.sub.5 atop a substrate; and b) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node; c) chemical vapor depositing a capacitor dielectric layer of Ta.sub.2 O.sub.5 over the first electrically conductive capacitor plate; and d) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.5, and "z" is in the range of from 0 to 0.3, with the sum of "x", "y" and "z" equalling about 1.0. Such is preferably deposited by utilizing a gaseous titanium organometallic precursor of the formula Ti(NR.sub.2).sub.4, where R is selected from the group consisting of H and a carbon containing radical, and utilizing deposition conditions of from 200.degree. C. to 600.degree. C. and from 0.1 to 100 Torr.

摘要翻译： 形成电介质层的方法包括：a）在衬底顶部化学气相沉积Ta 2 O 5的介电层; 和b）在Ta 2 O 5介电层上方提供主要的无定形扩散阻挡层。 形成电容器的方法包括：a）提供与电容器进行电连接的节点; b）在节点上提供第一导电电容器板; c）在第一导电电容器板上化学气相沉积Ta 2 O 5的电容器电介质层; 以及d）在Ta 2 O 5介电层上提供主要的非晶扩散阻挡层。 还公开了一种电容器结构。 优选的非晶扩散阻挡层是导电的，并且构成金属有机化学气相沉积TiC x N y O z，其中“x”在0.01至0.5的范围内，“y”在0.99至0.5的范围内，“z “在0至0.3的范围内，”x“，”y“和”z“之和等于约1.0。 优选通过使用式Ti（NR 2）4的气态钛有机金属前体，其中R选自H和含碳基团，并且使用200℃至600℃的沉积条件来沉积 和0.1至100乇。

公开(公告)号：US5902128A

公开(公告)日：1999-05-11

申请号：US733660

申请日：1996-10-17

申请人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan

发明人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan

IPC分类号： H01L21/762 ,  H01L21/94 ,  H01L21/76

CPC分类号： H01L21/76202

摘要： A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.

公开(公告)号：US5814852A

公开(公告)日：1998-09-29

申请号：US664305

申请日：1996-06-11

申请人： Gurtej S. Sandhu ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Pierre C. Fazan

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/62

CPC分类号： H01L28/56 ,  H01L28/40

摘要： A method of forming a dielectric layer includes, a) chemical vapor depositing a dielectric layer of Ta.sub.2 O.sub.5 atop a substrate; and b) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node; c) chemical vapor depositing a capacitor dielectric layer of Ta.sub.2 O.sub.5 over the first electrically conductive capacitor plate; and d) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.5, and "z" is in the range of from 0 to 0.3, with the sum of "x", "y" and "z" equalling about 1.0. Such is preferably deposited by utilizing a gaseous titanium organometallic precursor of the formula Ti(NR.sub.2).sub.4, where R is selected from the group consisting of H and a carbon containing radical, and utilizing deposition conditions of from 200.degree. C. to 600.degree. C. and from 0.1 to 100 Torr.

摘要翻译： 形成电介质层的方法包括：a）在衬底顶部化学气相沉积Ta 2 O 5的介电层; 和b）在Ta 2 O 5介电层上方提供主要的无定形扩散阻挡层。 形成电容器的方法包括：a）提供与电容器进行电连接的节点; b）在节点上提供第一导电电容器板; c）在第一导电电容器板上化学气相沉积Ta 2 O 5的电容器电介质层; 以及d）在Ta 2 O 5介电层上提供主要的非晶扩散阻挡层。 还公开了一种电容器结构。 优选的非晶扩散阻挡层是导电的，并且构成金属有机化学气相沉积TiC x N y O z，其中“x”在0.01至0.5的范围内，“y”在0.99至0.5的范围内，“z “在0至0.3的范围内，”x“，”y“和”z“之和等于约1.0。 优选通过使用式Ti（NR 2）4的气态钛有机金属前体，其中R选自H和含碳基团，并且使用200℃至600℃的沉积条件来沉积 和0.1至100乇。

公开(公告)号：US5798296A

公开(公告)日：1998-08-25

申请号：US649803

申请日：1996-05-17

申请人： Pierre C. Fazan ,  Hiang C. Chan

发明人： Pierre C. Fazan ,  Hiang C. Chan

IPC分类号： H01L21/28 ,  H01L29/49

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061

摘要： A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

公开(公告)号：US5702986A

公开(公告)日：1997-12-30

申请号：US567692

申请日：1995-12-05

申请人： Viju K. Mathews ,  Pierre C. Fazan ,  Nanseng Jeng

发明人： Viju K. Mathews ,  Pierre C. Fazan ,  Nanseng Jeng

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L21/84

CPC分类号： H01L29/6659 ,  H01L21/266 ,  H01L29/6656

摘要： This invention is a process flow involving wordline spacer formation and source/drain implants which mitigates stress-induced damage to the silicon substrate during the post-implant anneal step. The process employs composite wordline spacers having a removable silicon dioxide portion and a non-removable silicon nitride portion. The post-implant anneal step is performed with only the silicon nitride portion of the spacer in place on the wordlines. The thinness of the silicon nitride portion greatly reduces the stress levels experienced by the substrate during the anneal as compared with that experienced by the substrate when thick one-piece silicon nitride spacers are left in place during the anneal.

摘要翻译： 本发明是涉及字线间隔物形成和源/漏植入物的工艺流程，其在后植入退火步骤中减轻了对硅衬底的应力诱导的损伤。 该方法采用具有可去除的二氧化硅部分和不可移除的氮化硅部分的复合字线间隔物。 在字线上仅使用间隔物的氮化硅部分就位的植入后退火步骤。 氮化硅部分的薄度大大降低了退火期间衬底经历的应力水平，与在退火期间厚的一体式氮化硅间隔物留在原位时相比，衬底经历的应力水平相比。

公开(公告)号：US5658829A

公开(公告)日：1997-08-19

申请号：US551829

申请日：1995-11-07

申请人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan

发明人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/14 ,  H01L23/522

CPC分类号： H01L21/76843 ,  H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002

摘要： A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer of conductive material atop the wafer and to within the facet etched contact opening to fill the contact opening; and h) etching the conductive material and first material layer inwardly to at least the angled sidewalls' inner base to define an electrically conductive contact plug which electrically connects with the substrate.

摘要翻译： 相对于晶片形成导电接触插塞的半导体处理方法包括：a）提供要进行电连接的基板; b）在基板顶部沉积一层第一材料至所选择的厚度; c）图案掩蔽第一材料层以形成所需的接触开口; d）蚀刻通过第一材料层以形成通过其与基板电连接的接触开口，接触开口具有最外区域; e）在蚀刻之后形成接触开口，从第一材料层去除掩模; f）在从第一材料层去除掩模之后，相对于接触开口小面溅射蚀刻到第一材料层中以提供向外成角度的侧壁，这有效地加宽了接触开口最外区域，向外成角度的侧壁具有内部基部， 与原来的接触开口; g）在晶片顶部和面蚀刻的接触开口内沉积导电材料层以填充接触开口; 以及h）将所述导电材料和所述第一材料层向内蚀刻到至少所述成角度的侧壁的内部基底，以限定与所述基底电连接的导电接触插塞。

公开(公告)号：US5629230A

公开(公告)日：1997-05-13

申请号：US509782

申请日：1995-08-01

申请人： Pierre C. Fazan ,  Nanseng Jeng ,  David L. Dickerson

发明人： Pierre C. Fazan ,  Nanseng Jeng ,  David L. Dickerson

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/76202

摘要： A semiconductor processing method of forming a field oxide region on a semiconductor substrate includes, a) providing a patterned first masking layer over a desired active area region of a semiconductor substrate, the first masking layer having at least one side edge; b) providing a silicon sidewall spacer over the side edge of the patterned first masking layer, the silicon sidewall spacer having a laterally outward projecting foot portion; c) oxidizing the substrate and the silicon sidewall spacer to form a field oxide region on the substrate; d) stripping the first masking layer from the substrate; and e) providing a gate oxide layer over the substrate. The invention enables taking advantage of process techniques which minimize the size of field oxide bird's beaks without sacrificing upper field oxide topography.

摘要翻译： 在半导体衬底上形成场氧化物区域的半导体处理方法包括：a）在半导体衬底的期望的有源区域上提供图案化的第一掩模层，所述第一掩模层具有至少一个侧边; b）在图案化的第一掩蔽层的侧边缘上提供硅侧壁间隔物，硅侧壁间隔件具有横向向外突出的脚部; c）氧化所述衬底和所述硅侧壁间隔物以在所述衬底上形成场氧化物区域; d）从衬底剥离第一掩蔽层; 以及e）在所述衬底上提供栅氧化层。 本发明能够利用在不牺牲上部场氧化物形貌的情况下使场氧化物鸟的喙的尺寸最小化的工艺技术。

公开(公告)号：US5624865A

公开(公告)日：1997-04-29

申请号：US542979

申请日：1995-10-13

申请人： Klaus F. Schuegraf ,  Randhir P. S. Thakur ,  Pierre C. Fazan

发明人： Klaus F. Schuegraf ,  Randhir P. S. Thakur ,  Pierre C. Fazan

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/1085 ,  H01L28/40

摘要： A semiconductor integrated circuit fabrication method is provided for forming a capacitor on a semiconductor integrated circuit substrate. A lower capacitor electrode is formed over the semiconductor integrated circuit substrate and a capacitor dielectric is formed over the lower capacitor electrode. The capacitor dielectric is preferably formed of silicon nitride. A reoxidation anneal of the capacitor dielectric is performed at a pressure greater than one atmosphere in order to form an oxide layer over the capacitor dielectric. An upper capacitor electrode is disposed over the oxide layer to form a capacitor. The capacitor is formed as part of a dynamic random access memory cell. A transistor is formed upon the semiconductor integrated circuit substrate and the lower capacitor electrode is formed in electrical contact with a diffusion region of the transistor. The capacitor is formed within an opening in molding material that is deposited over the surface of the semiconductor integrated circuit substrate. The reoxidization anneal of the capacitor dielectric is performed at a temperature in the range of 600.degree. C. to 800.degree. C. at pressures ranging up to twenty-five atmospheres. This forms an oxide layer having a thickness between five angstroms and fifteen angstroms in a period of time short enough to prevent excessive out diffusion of dopants from the diffusion regions of the transistor.

摘要翻译： 提供半导体集成电路制造方法，用于在半导体集成电路基板上形成电容器。 在半导体集成电路基板上形成下电容电极，在下电容器电极上形成电容电介质。 电容器电介质优选由氮化硅形成。 电容器电介质的再氧化退火在大于1个大气压的压力下进行，以便在电容器电介质上形成氧化物层。 上电容器电极设置在氧化物层上以形成电容器。 电容器形成为动态随机存取存储器单元的一部分。 晶体管形成在半导体集成电路基板上，而下电容器电极形成为与晶体管的扩散区域电接触。 电容器形成在沉积在半导体集成电路基板的表面上的成型材料的开口内。 电容器电介质的再氧化退火在高达二十五个大气压的压力下在600℃至800℃的温度范围内进行。 这形成了在足够短的时间内形成厚度在五埃至十五埃之间的氧化物层，以防止掺杂剂从晶体管的扩散区过度扩散。