公开(公告)号：US5973373A

公开(公告)日：1999-10-26

申请号：US817630

申请日：1997-03-26

申请人： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann ,  Wolfgang Rosner

发明人： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann ,  Wolfgang Rosner

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11273 ,  H01L27/112

摘要： A read-only-memory cell arrangement comprises memory cells, each having a vertical MOS transistor, in a substrate (21) made of semiconductor material, the various logic values (zero, one) being implemented by gate dielectrics (27, 28) of different thickness. The memory cell arrangement can preferably be produced in a silicon substrate, with a small number of process steps and a high packing density. The memory cell arrangement and a drive circuit for read-out can in this case be produced in an integrated manner.

摘要翻译： PCT No.PCT / DE95 / 01262 Sec。 371日期1997年3月26日 102（e）1997年3月26日PCT PCT 1995年9月14日PCT公布。 公开号WO96 / 10266 日期1996年4月4日只读存储单元布置包括在由半导体材料制成的衬底（21）中的每个具有垂直MOS晶体管的存储单元，各种逻辑值（零，1）由栅极电介质 27,28）。 存储单元布置可以优选地在硅衬底中制造，具有少量的工艺步骤和高的堆积密度。 在这种情况下，存储单元布置和用于读出的驱动电路可以以集成的方式产生。

公开(公告)号：US5959328A

公开(公告)日：1999-09-28

申请号：US779446

申请日：1997-01-07

申请人： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann ,  Hans Reisinger

发明人： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann ,  Hans Reisinger

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： An electrically programmable memory cell arrangement has a plurality of individual memory cells that respectively has an MOS transistor with a gate dielectric with traps, and which are arranged in rows that run in parallel. Adjacent rows thereby respectively run in alternating fashion on the bottom of the longitudinal trenches (5) and between adjacent longitudinal trenches (5) and are insulated against one another. The memory cell arrangement can be manufactured by means of self-adjusting process steps with a surface requirement per memory cell of 2 F.sup.2 (F: minimum structural size).

摘要翻译： 电可编程存储单元布置具有多个单独的存储单元，它们分别具有带栅极电介质的MOS晶体管，并具有陷阱，并且它们排列成并行的行。 因此，相邻的行分别以纵向沟槽（5）的底部和相邻的纵向沟槽（5）之间交替地延伸并彼此绝缘。 可以通过自调整工艺步骤制造存储单元布置，每个存储单元的表面要求为2×2（F：最小结构尺寸）。

公开(公告)号：US5736761A

公开(公告)日：1998-04-07

申请号：US645503

申请日：1996-05-14

申请人： Lothar Risch ,  Franz Hofmann ,  Wolfgang Roesner ,  Wolfgang Krautschneider

发明人： Lothar Risch ,  Franz Hofmann ,  Wolfgang Roesner ,  Wolfgang Krautschneider

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.

摘要翻译： DRAM单元布置对每个存储单元具有一个垂直MOS晶体管，其第一源极/漏极区域邻接沟槽位线（5），其栅极电极（13）与沟槽字线连接，并且其第二源极/漏极区域（3）邻接 基板主表面（1）。 至少在第二源极/漏极区域上布置有特别是铁电体或者顺电层的电容器电介质（16），并且电容器板（17）布置在电介质上，使得第二源极/漏极区域 3）另外作为存储器节点。 可以利用4F2的存储单元表面来制造DRAM单元布置。

公开(公告)号：US5977589A

公开(公告)日：1999-11-02

申请号：US191482

申请日：1998-11-13

申请人： Till Schloesser ,  Wolfgang Krautschneider

发明人： Till Schloesser ,  Wolfgang Krautschneider

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/72

CPC分类号： H01L27/10844 ,  H01L27/108

摘要： A memory cell containing at least three vertical transistors. A first transistor and a second transistor, or a third transistor are arranged over each other with reference to a y-axis proceeding perpendicularly to a surface of a substrate. The second transistor and the third transistor can be arranged at opposite sides of a semiconductor structure, while the first transistor is arranged at both sides. Source/drain regions of the transistors can overlap.

摘要翻译： 一个包含至少三个垂直晶体管的存储单元。 相对于垂直于衬底表面的y轴，第一晶体管和第二晶体管或第三晶体管彼此相互排列。 第二晶体管和第三晶体管可以布置在半导体结构的相对侧，而第一晶体管布置在两侧。 晶体管的源/漏区可以重叠。

公开(公告)号：US5854500A

公开(公告)日：1998-12-29

申请号：US721546

申请日：1996-09-26

申请人： Wolfgang Krautschneider

发明人： Wolfgang Krautschneider

IPC分类号： H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/108 ,  H01L27/0629

摘要： A dynamic gain memory cell of a DRAM cell array includes a planar MOS transistor as a selection transistor and a vertical MOS transistor as a memory transistor, which are connected to one another via a common source/drain region. The memory transistor has a gate electrode of doped silicon, which is disposed along at least one side of a trench. In the trench, an oppositely doped silicon structure is provided, which with the gate electrode of the memory transistor forms a diode, which is connected to the common source/drain region via a contact.

摘要翻译： DRAM单元阵列的动态增益存储单元包括作为选择晶体管的平面MOS晶体管和作为存储晶体管的垂直MOS晶体管，其经由公共源极/漏极区彼此连接。 存储晶体管具有掺杂硅的栅极，其沿着沟槽的至少一侧设置。 在沟槽中，提供相反掺杂的硅结构，其与存储晶体管的栅电极形成二极管，其通过触点连接到公共源/漏区。

公开(公告)号：US5646883A

公开(公告)日：1997-07-08

申请号：US708913

申请日：1996-09-05

申请人： Wolfgang Krautschneider ,  Klaus J. Lau

发明人： Wolfgang Krautschneider ,  Klaus J. Lau

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/402 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/00

CPC分类号： G11C7/065 ,  G11C11/404 ,  G11C11/4091

摘要： A memory system includes a plurality of gain memory cells connected via bit bits to sense amplifiers with each sense amplifier having at least two pairs of metal oxide semiconductor (MOS) transistors which have opposite conductivity types. Each gain memory cell has two serially connected n-channel MOS transistors with a diode connected between a gate of a first of the transistors and a source thereof. Three illustrative embodiments of sense amplifiers are used with the gain memory cells.

摘要翻译： 存储器系统包括通过比特位连接到读出放大器的多个增益存储单元，每个读出放大器具有至少两对具有相反导电类型的金属氧化物半导体（MOS）晶体管。 每个增益存储单元具有两个串联连接的n沟道MOS晶体管，二极管连接在第一晶体管的栅极和源极之间。 读出放大器的三个说明性实施例与增益存储单元一起使用。

公开(公告)号：US06274431B1

公开(公告)日：2001-08-14

申请号：US09301108

申请日：1999-04-28

申请人： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

发明人： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

IPC分类号： H01L2976

CPC分类号： H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66666

摘要： An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

摘要翻译： 集成电路装置包含由绝缘结构围绕的MOS晶体管，其源极和漏极横向排列并且在不同的深度。 其通道基本上垂直于电路装置的表面。 由于通过蚀刻或通过生长层来确定沟道长度，所以可以实现短于小于50nm的沟道长度。 为了制造，采用其中集成平面晶体管的传统电路布置的大多数掩模，这显着地有助于结合到半导体制造中。

公开(公告)号：US6066876A

公开(公告)日：2000-05-23

申请号：US65173

申请日：1998-04-23

申请人： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

发明人： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/4236

摘要： An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

摘要翻译： 集成电路装置包含由绝缘结构包围的MOS晶体管，其源极和漏极横向设置在不同的深度。 其通道基本上垂直于电路装置的表面。 由于通过蚀刻或通过生长层来确定沟道长度，所以可以实现短于小于50nm的沟道长度。 为了制造，采用其中集成平面晶体管的传统电路布置的大多数掩模，这显着地有助于结合到半导体制造中。

公开(公告)号：US5327374A

公开(公告)日：1994-07-05

申请号：US956896

申请日：1992-12-29

申请人： Wolfgang Krautschneider ,  Klaus Lau ,  Lothar Risch

发明人： Wolfgang Krautschneider ,  Klaus Lau ,  Lothar Risch

IPC分类号： H01L27/10 ,  G11C5/00 ,  G11C11/402 ,  G11C11/404 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C11/405 ,  G11C11/404 ,  G11C5/005 ,  H01L27/108

摘要： An arrangement with self-amplifying dynamic MOS transistor storage cells has in each case a MOS selection transistor AT, whose gate is connected to a word line WL, and an MOS storage transistor ST at whose gate a capacitor C for charge storage acts. This self-amplifying storage cell can be written on and read out with only one bit line BL and one word line WL. The two transistors AT and ST are connected in series and a common drain source region DS is connected via a voltage-dependent resistor VR to the gate electrode GST of the control transistor. The advantages reside in the fact that the cell geometry can be scaled without at the same time the quantity Q of charge which can be read out on the bit line BL having to be reduced, in that the quantity Q of charge which can be read out is larger than a charge stored in the capacitor C which acts at the gate of the storage transistor ST and in that the two MOS transistors AT and ST can be produced relatively simply.

摘要翻译： PCT No.PCT / DE91 / 00502 Sec。 371日期1992年12月29日 102（e）1992年12月29日PCT PCT 1991年7月18日PCT公布。 公开号WO92 / 01287 日本1992年1月23日。具有自放大动态MOS晶体管存储单元的布置在每种情况下都是MOS选择晶体管AT，其栅极连接到字线WL，MOS存储晶体管ST在其栅极处具有电容器C 用于充电存储动作。 该自放大存储单元可以仅用一个位线BL和一个字线WL写入和读出。 两个晶体管AT和ST串联连接，并且公共漏极源极区域DS经由电压依赖电阻器VR连接到控制晶体管的栅电极GST。 优点在于，可以对单元几何形状进行缩放，而不必同时在位线BL上读出的电荷量Q必须减小，因为可以读出的电荷量Q 大于存储在存储晶体管ST的栅极处的电容器C中存储的电荷，并且可以相对简单地制造两个MOS晶体管AT和ST。

公开(公告)号：US06184045B2

公开(公告)日：2001-02-06

申请号：US09541952

申请日：2000-04-03

申请人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

发明人： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

摘要翻译： 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。