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公开(公告)号：US20070300096A1
公开(公告)日：2007-12-27
申请号：US11426671
申请日：2006-06-27
IPC分类号： G06F1/12
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译： 双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。 数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。 例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时 在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。
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公开(公告)号：US20070300032A1
公开(公告)日：2007-12-27
申请号：US11426675
申请日：2006-06-27
IPC分类号： G06F13/00
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译： 一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。 数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。 有很多应用程序。 在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。
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公开(公告)号：US07266737B2
公开(公告)日：2007-09-04
申请号：US11180416
申请日：2005-07-13
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G01R31/318533 , G11C29/88 , G11C2029/3202
摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.
摘要翻译： 扫描能够用RAM和关联电路的无缺陷备用元件替换缺陷存储器元件和相关电路的半导体存储器电路，以便在修复RAM之前更换有缺陷的RAM元件。 耦合一组置位/复位锁存器以接收来自存储器元件的信号，以及多路复用器控制电路，其被耦合以从多路复用器接收移位信号和ram_inhibit信号以向多路复用器部件提供特定的输入信号。 当扫描操作开始时，活动时钟信号将设置/复位锁存器设置为ram_inhibit模式，并且阻止存储器元件影响存储器输出锁存器的状态，由此当存储器操作开始时，有源时钟信号将复位置位/复位 锁存到系统模式以使多路复用器将适当的信号从存储器元件传递到输出锁存器，并且备用存储器元件被激活以替换有缺陷的存储器元件。
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公开(公告)号：US20070033459A1
公开(公告)日：2007-02-08
申请号：US11180416
申请日：2005-07-13
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/318533 , G11C29/88 , G11C2029/3202
摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.
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35.发明授权公开(公告)号：US06460157B1
公开(公告)日：2002-10-01
申请号：US09450548
申请日：1999-11-30
IPC分类号： H03M1300
CPC分类号： G06F11/1008 , G11B20/18
摘要： Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.
摘要翻译： 数据在从一个或多个源纠错码到一个或多个目的地纠错码的转换期间通过在检测到源纠错码中的错误之前产生目的地纠错码的检查位来保护。 在开始生成这些校验位之后，检测源纠错码中的任何错误。 通过补充目的地纠错码的错误位，随后在目的地纠错码中校正这些误差。 此外，还可以实现各种逻辑降低技术以提高效率。
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公开(公告)号：US5692209A
公开(公告)日：1997-11-25
申请号：US484771
申请日：1995-06-07
CPC分类号： G06F9/5011 , G06F1/32 , G06F13/18 , G06F2209/507 , Y02B60/142
摘要： A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.
摘要翻译： 一种系统资源使能装置，用于对包括代表资源当前和未来操作的寄存器的系统资源进行操作，模式生成器，将与所请求的资源操作相对应的模式应用于队列中的资源操作的多个请求中的每一个 比较逻辑，如果请求将与其他资源操作冲突，则通过将应用于该请求的模式与该寄存器进行比较来确定多个请求中的每个请求，优先级授权逻辑如果没有确定冲突则向队列中的请求授予优先权 并根据应用于请求的模式来更新寄存器，以及根据寄存器对资源进行操作的资源使能逻辑。
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公开(公告)号：US08914708B2
公开(公告)日：2014-12-16
申请号：US13523971
申请日：2012-06-15
CPC分类号： H03M13/05 , G06F11/073 , G06F11/1008 , G06F11/1064 , G06F11/1666 , G06F11/20
摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.
摘要翻译： 提供了一种错误检测技术。 控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。 控制器检测读取的字线的ECC字中的错误。 控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。 控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。
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38.发明授权Collecting failure information on error correction code (ECC) protected data 有权收集有关纠错码（ECC）保护数据的故障信息公开(公告)号：US08316284B2
公开(公告)日：2012-11-20
申请号：US12360402
申请日：2009-01-27
CPC分类号： G06F11/10
摘要： Methods of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
摘要翻译： 纠错码（ECC）调试方法可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。 该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。 该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。
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39.发明申请CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES 失效在存在的存储器件故障存在的情况下修正存储器件和存储器通道故障公开(公告)号：US20120198309A1
公开(公告)日：2012-08-02
申请号：US13016977
申请日：2011-01-29
CPC分类号： G06F11/10 , H03M13/13 , H03M13/1515 , H03M13/152 , H03M13/19
摘要： Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.
摘要翻译： 在存在已知存储器件故障的情况下更正存储器件（芯片）和存储器通道故障。 存储器通道故障被定位和校正，或者高达c个芯片故障被校正，并且在存在被标记为可疑的最多u个芯片的情况下，检测到高达d个芯片故障。 执行解码的第一阶段，其导致恢复影响数据的可校正错误的估计或者宣告不可校正的错误状态。 当声明不可校正的错误状态时，执行第二级解码以尝试在每次迭代中改变通道位置的M次迭代中纠正擦除和通道错误。 响应正好一个M次迭代成功声明可纠正的错误。
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40.发明申请CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS 有权CHANNEL MARKING FOR CHIP MARK OVERFLOW和CALIBRATION ERRORS公开(公告)号：US20120173936A1
公开(公告)日：2012-07-05
申请号：US12981017
申请日：2010-12-29
IPC分类号： G06F11/10
CPC分类号： G11C29/44 , G06F11/1044 , G06F11/1076 , G06F11/30 , G06F2211/1064
摘要： Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.
摘要翻译： 当从存储器芯片的数据中检测到故障时，将存储器芯片标记为故障。 在检测到多个存储器芯片有故障时，确定多个存储器通道中的哪一个存储有故障的存储器芯片。 响应于确定故障存储器芯片的数量已经超过阈值，将多个存储器通道中的一个标记为失败。
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