公开(公告)号：US20230282643A1

公开(公告)日：2023-09-07

申请号：US17685025

申请日：2022-03-02

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78642 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/66742

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of channel layers positioned over a substrate, where the channel layers are spaced apart from one another. The semiconductor device includes source/drain (S/D) structures positioned at a first side and a second side of the stack of channel layers and in contact with the channel layers, where the first side is opposite to the second side. The semiconductor device includes gate dielectric layers arranged around the channel layers, and gate electrodes surrounding the gate dielectric layers and further extending from a third side and a fourth side of the stack of channel layers, where the third side is opposite to the fourth side. The semiconductor device further includes a seed layer positioned over the stack of channel layers.

公开(公告)号：US20230246031A1

公开(公告)日：2023-08-03

申请号：US17592095

申请日：2022-02-03

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/66666 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823885

Abstract: Aspects of the present disclosure provide a 3D semiconductor structure and a method for fabricating the same. The 3D semiconductor structure can include a vertical field-effect transistor (VFET). The VFET can include a lower source/drain (S/D) region, a channel formed on the lower S/D region, a gate region surrounding the channel, and an upper S/D region formed on the channel. One of the lower and upper S/D regions can include a channel material having a graded dopant profile. The VFET can further include lower and upper S/D electrodes coupled to the lower and upper S/D regions, respectively, a gate electrode coupled to the gate region, a lower S/D spacer formed between the lower S/D electrode and the gate electrode, and an upper S/D spacer formed between the gate electrode and the upper S/D electrode. The upper S/D spacer can have a different thickness from the lower S/D spacer.

公开(公告)号：US20230207397A1

公开(公告)日：2023-06-29

申请号：US17884192

申请日：2022-08-09

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/84 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/76251 ,  H01L27/1203

Abstract: A method of fabricating a semiconductor device includes receiving a first wafer including a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer. The first SOI stack includes a first semiconductor. A second wafer is received that includes a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer. The second SOI stack includes a second semiconductor. The front side of the first wafer is bonded to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer. The second substrate is removed. A stack of transistor devices is formed with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.

公开(公告)号：US20230161267A1

公开(公告)日：2023-05-25

申请号：US17888553

申请日：2022-08-16

Applicant: Tokyo Electron Limited

Inventor： Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  Anton J. DEVILLIERS ,  H. Jim FULFORD

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70625

Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.

公开(公告)号：US20220238652A1

公开(公告)日：2022-07-28

申请号：US17490182

申请日：2021-09-30

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/20

Abstract: A microfabricated transistor device includes a vertical stack of two or more channels of field effect transistors on a semiconductor substrate. Each of the channels has a vertical conductive path relative to a surface of the semiconductor substrate. At least one of the channels includes a shell formed around a core material, the shell including epitaxial material. The vertical stack can include a channel for a PMOS field effect transistor, and a channel for an NMOS field effect transistor.

公开(公告)号：US20220115271A1

公开(公告)日：2022-04-14

申请号：US17557561

申请日：2021-12-21

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Anton DEVILLIERS

IPC: H01L21/768 ,  H01L21/306 ,  H01L23/48 ,  H01L21/822 ,  H01L23/532

Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.

公开(公告)号：US20220077003A1

公开(公告)日：2022-03-10

申请号：US16951125

申请日：2020-11-18

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/8238

Abstract: Aspects of the present disclosure provide a method for fabricating a 3D semiconductor apparatus. The method can include forming a multilayer stack including a plurality of dielectric layers. The dielectric layers can include three or four dielectric materials that can be etched selectively with respect to one another. The method can also include forming opening(s) in the multilayer stack, and filling the opening(s) with first and second channel materials to form first and second channels that interface at a transition dielectric layer the multilayer stack. The method can also include removing second and first source/drain (S/D) dielectric layers of the multilayer stack and replacing with second and first S/D materials to form second and first S/D regions, respectively. The method can also include removing gate dielectric layers of the multilayer stack and replacing with a gate material to form gate regions of the 3D semiconductor apparatus.

公开(公告)号：US20210217666A1

公开(公告)日：2021-07-15

申请号：US17123987

申请日：2020-12-16

Applicant: TOKYO ELECTRON LIMITED

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor device includes a first n-type transistor and a first p-type transistor that are positioned side by side over a substrate. The first n-type transistor includes a first n-type source/drain (S/D) region, a first n-type channel region, and a second n-type S/D region that are formed based on a first continuous channel structure extending along a horizontal direction parallel to the substrate. The first n-type channel region is positioned between the first n-type S/D region and the second n-type S/D region. The first p-type transistor includes a first p-type S/D region, a first p-type channel region, and a second p-type S/D region that are formed based on the first continuous channel structure. The first p-type channel region is positioned between the first p-type S/D region and the second p-type S/D region. The second n-type S/D region is in contact with the first p-type S/D region.

公开(公告)号：US20210202481A1

公开(公告)日：2021-07-01

申请号：US17136820

申请日：2020-12-29

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Anton J. DEVILLIERS ,  Mark I. GARDNER ,  Daniel CHANEMOUGAME ,  Jeffrey SMITH ,  Lars LIEBMANN ,  Subhadeep KAL

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/16 ,  H01L21/8238

Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.

公开(公告)号：US20210175327A1

公开(公告)日：2021-06-10

申请号：US16848738

申请日：2020-04-14

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Anton J. DEVILLIERS

IPC: H01L29/06 ,  H01L21/822 ,  H01L21/8239 ,  H01L21/02

Abstract: Transistor/semiconductor devices and methods of forming transistor/semiconductor devices. The devices include a metal layer with dielectric isolation within existing 3D silicon stacks. Two different disposable materials within the 3D silicon stack are selectively removed later from other layers in the stack to become future metal layers and oxide layer respectively, to provide the metal line isolated in a vertical central portion of the stack.