利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

72 条记录 (耗时 0.034 秒)

    Tissue extraction device and method of using the same
    32.
    发明申请
    Tissue extraction device and method of using the same 审中-公开
    组织提取装置及其使用方法

    公开(公告)号：US20080058674A1

    公开(公告)日：2008-03-06

    申请号：US11511531

    申请日：2006-08-29

    申请人： Lex Jansen ,  Art Ferdinand ,  Hugues F. Malandain ,  Claudia Orellana ,  Chris Phan ,  Derek Rothwell ,  Jennifer Wong

    发明人： Lex Jansen ,  Art Ferdinand ,  Hugues F. Malandain ,  Claudia Orellana ,  Chris Phan ,  Derek Rothwell ,  Jennifer Wong

    IPC分类号： A61B10/00

    CPC分类号： A61B10/0266 ,  A61B10/025 ,  A61B10/04 ,  A61B2017/00867

    摘要： Apparatuses and methods for performing minimally invasive medical procedures are disclosed herein. In one example, an apparatus includes an elongate body that has a deformable distal portion and defines a lumen, the lumen extends through the deformable distal portion. The deformable distal portion has a cutting portion and defines an opening. The elongate body has a first configuration in which the opening is a first size and a second configuration in which the opening is a second size smaller than the first size of the opening. The elongate body in the first configuration is configured to be percutaneously inserted at least partially into a tissue such that at least a portion of the tissue is disposed within the lumen. The elongate body is configured to move to the second configuration when the elongate body reaches a threshold temperature while inserted in the tissue.

    摘要翻译： 本文公开了用于执行微创医疗程序的装置和方法。 在一个示例中，设备包括具有可变形的远侧部分并限定内腔的细长主体，内腔延伸穿过可变形远端部分。 可变形远端部分具有切割部分并限定开口。 细长体具有第一构造，其中开口是第一尺寸和第二构造，其中开口是小于开口的第一尺寸的第二尺寸。 第一构造中的细长体构造成至少部分地经皮地插入到组织中，使得组织的至少一部分设置在内腔内。 细长体构造成当细长体在插入组织中时达到阈值温度时移动到第二构型。

    Digital signal processing block having a wide multiplexer
    35.
    发明申请
    Digital signal processing block having a wide multiplexer 有权
    具有宽多路复用器的数字信号处理块

    公开(公告)号：US20060212499A1

    公开(公告)日：2006-09-21

    申请号：US11433120

    申请日：2006-05-12

    申请人： Bernard New ,  Vasisht Vadi ,  Jennifer Wong ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  James Simkins

    发明人： Bernard New ,  Vasisht Vadi ,  Jennifer Wong ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  James Simkins

    IPC分类号： G06F15/00

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

    摘要翻译： 一种数字信号处理块，具有：1）第一数字信号处理元件，包括：第一多路复用器的第一多路复用器，所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元，所述第一算术逻辑单元被配置为用于相加; 以及2）第二数字信号处理元件，包括：第二多路复用器的第二多路复用器，所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器，所述第二运算单元被配置为相加。

    Method and apparatus for discriminating against signal interference
    36.
    发明授权
    Method and apparatus for discriminating against signal interference 有权
    用于区分信号干扰的方法和装置

    公开(公告)号：US06353341B1

    公开(公告)日：2002-03-05

    申请号：US09439844

    申请日：1999-11-12

    申请人： Austin H. Lesea ,  Peter H. Alfke ,  Jennifer Wong ,  Steven P. Young

    发明人： Austin H. Lesea ,  Peter H. Alfke ,  Jennifer Wong ,  Steven P. Young

    IPC分类号： G01R2902

    CPC分类号： G01R31/31922 ,  G01R31/31937

    摘要： A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

    摘要翻译： 监视时钟信号以检测从第一逻辑状态到第二逻辑状态的转变。 一旦检测到该转变，则在时间信号的后续转换在信号干扰最显着的预定时间段期间被忽略。 在经过预定时间段之后，再次监视时钟信号以检测随后的状态转换。 在一些实施例中，使用延迟电路来延迟时钟信号以产生延迟的时钟信号，该延迟时钟信号用于将时钟信号强制到第二逻辑状态达预定时间段。 在一个实施例中，通过延迟电路上的一个或多个可选择的抽头，预定时间段是用户可选择的。

    Method of time multiplexing a programmable logic device
    37.
    发明授权
    Method of time multiplexing a programmable logic device 失效

    公开(公告)号：US5978260A

    公开(公告)日：1999-11-02

    申请号：US119534

    申请日：1998-07-20

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G06F17/50 ,  G11C5/00 ,  H03K19/177 ,  G11C13/00

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

    Low voltage interface circuit with a high voltage tolerance
    38.
    发明授权
    Low voltage interface circuit with a high voltage tolerance 失效
    具有高电压容差的低压接口电路

    公开(公告)号：US5933025A

    公开(公告)日：1999-08-03

    申请号：US784163

    申请日：1997-01-15

    申请人： Scott S. Nance ,  Mohammad R. Tamjidi ,  Richard C. Li ,  Jennifer Wong ,  Hassan K. Bazargan

    发明人： Scott S. Nance ,  Mohammad R. Tamjidi ,  Richard C. Li ,  Jennifer Wong ,  Hassan K. Bazargan

    IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/094

    CPC分类号： H03K19/09429 ,  H03K19/00315 ,  H03K19/018521

    摘要： A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin. In high impedance mode when the externally applied voltage at the I/O pin is sufficiently below the interface circuit supply voltage, the isolation circuit is driven to approximately the interface circuit supply voltage. In low impedance mode the isolation circuitry is disabled and the logic level at the data terminal is transmitted to the I/O pin. One embodiment of the present invention provides a buffered data path from the data terminal to the I/O pin.

    摘要翻译： 具有高电压公差的低压接口电路使得具有不同电源电平的器件能够有效耦合在一起，而不会有明显的漏电流或电路损坏。 本发明的一个实施例包括三态控制电路，数据通路，参考电压电路和隔离电路。 接口电路提供高阻抗接收模式。 在这种模式下，当接口电路的I / O引脚施加的电压足够大于接口电路电源电压时，隔离电路会将电源与I / O引脚隔离开来。 接口电路还保护所有的晶体管从栅极到体积，栅极到源极和漏极到大于指定电压的电压降，例如对于额定3V电源的3.6V，当高达5.5V被外部施加到 I / O引脚。 在高阻抗模式下，当I / O引脚的外部施加电压足够低于接口电路电源电压时，隔离电路被驱动到大致接口电路电源电压。 在低阻模式下，隔离电路被禁用，数据端子的逻辑电平被传输到I / O引脚。 本发明的一个实施例提供从数据终端到I / O引脚的缓冲数据路径。