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    Oxide semiconductor field effect transistor device and method for manufacturing the same
    32.
    发明授权
    Oxide semiconductor field effect transistor device and method for manufacturing the same 有权
    氧化物半导体场效应晶体管器件及其制造方法

    公开(公告)号：US09455351B1

    公开(公告)日：2016-09-27

    申请号：US14841731

    申请日：2015-09-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu

    IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417

    CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/66969

    Abstract: An oxide semiconductor field effect transistor (OS FET) device includes a first dielectric layer formed on a substrate, an oxide semiconductor (OS) island formed on the first dielectric layer, a first gate electrode formed on the OS island, a gate dielectric layer formed in between the first gate electrode and the OS island, a patterned hard mask layer formed on a top surface of the first gate electrode, an etch stop layer covering a top surface of the patterned hard mask layer and sidewalls of the first gate electrode, and a source electrode and a drain electrode formed on the OS island. At least one of the source electrode and the drain electrode partially overlaps the etching stop layer on the sidewalls of the first gate electrode.

    Abstract translation: 一种氧化物半导体场效应晶体管（OS FET）器件包括形成在基板上的第一介电层，形成在第一介电层上的氧化物半导体（OS）岛，形成在OS岛上的第一栅电极，形成的栅介质层 在第一栅电极和OS岛之间，形成在第一栅电极的顶表面上的图案化硬掩模层，覆盖图案化硬掩模层的顶表面和第一栅电极的侧壁的蚀刻停止层，以及 形成在OS岛上的源电极和漏电极。 源极电极和漏极电极中的至少一个部分地与第一栅电极的侧壁上的蚀刻停止层重叠。

    Semiconductor apparatus with multi-layer capacitance structure
    33.
    发明授权
    Semiconductor apparatus with multi-layer capacitance structure 有权
    具有多层电容结构的半导体装置

    公开(公告)号：US09305994B2

    公开(公告)日：2016-04-05

    申请号：US14445416

    申请日：2014-07-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  H01L28/60

    Abstract: A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.

    Abstract translation: 提供了包括堆叠电容结构的半导体装置。 堆叠的电容结构包括具有与第一内金属层的边缘相邻的第一焊盘区域的第一内部金属层，设置在第一内部金属层上并暴露第一焊盘区域的第一绝缘层，设置的第二内部金属层 在第一绝缘层上并且具有与第二内金属层的边缘相邻的第二焊盘区域，设置在第二内金属层上并暴露第二焊盘区域的第二绝缘层，以及覆盖第二内金属层的第三内金属层 金属层并且包括至少一个第一狭缝。 第一焊盘区域和第二焊盘区域包括多个焊盘。 第一狭缝对应于第二焊盘区域，使得第二焊盘区域上的焊盘露出。

    Integrated circuit and method of forming integrated circuit
    35.
    发明授权
    Integrated circuit and method of forming integrated circuit 有权
    集成电路和形成集成电路的方法

    公开(公告)号：US09064719B1

    公开(公告)日：2015-06-23

    申请号：US14324090

    申请日：2014-07-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

    IPC: H01L23/52 ,  H01L27/06 ,  H01L27/12

    CPC classification number: H01L27/0688 ,  H01L27/0629 ,  H01L27/0682 ,  H01L27/1203 ,  H01L2224/48247

    Abstract: An integrated circuit includes a capacitor and a non-inductive resistor. A substrate has a capacitor area and a resistor area. A patterned stacked structure including a bottom conductive layer, an insulating layer and a top conductive layer from bottom to top is sandwiched by a first dielectric layer and a second dielectric layer disposed on the substrate. A first metal plug and a second metal plug contact the top conductive layer and the bottom conductive layer of the capacitor area respectively, thereby the patterned stacked structure in the capacitor area constituting the capacitor. A third metal plug and a fourth metal plug contact the bottom conductive layer and the top conductive layer of the resistor area respectively, and a fifth metal plug contacts the bottom conductive layer and the top conductive layer of the resistor area simultaneously, thereby the patterned stacked structure in the resistor area constituting the non-inductive resistor.

    Abstract translation: 集成电路包括电容器和非感性电阻器。 衬底具有电容器区域和电阻器区域。 包括底部导电层，绝缘层和从顶部到顶部的顶部导电层的图案化堆叠结构被设置在基板上的第一介电层和第二介电层夹在中间。 第一金属插塞和第二金属插头分别与电容器区域的顶部导电层和底部导电层接触，从而构成电容器区域中的图案化堆叠结构。 第三金属插塞和第四金属插头分别接触电阻器区域的底部导电层和顶部导电层，并且第五金属插头同时接触电阻器区域的底部导电层和顶部导电层，由此图案化堆叠 构成无感电阻器的电阻区域的结构。

    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
    37.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20190027607A1

    公开(公告)日：2019-01-24

    申请号：US16131014

    申请日：2018-09-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

    IPC: H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L27/12 ,  H01L29/24 ,  H01L29/06 ,  H01L29/04

    Abstract: The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.

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