公开(公告)号：US20240162208A1

公开(公告)日：2024-05-16

申请号：US18077192

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L25/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/18 ,  H03H3/08 ,  H03H9/02

CPC classification number: H01L25/167 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/454 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786 ,  H01L31/022408 ,  H01L31/03044 ,  H01L31/035236 ,  H01L31/1856 ,  H03H3/08 ,  H03H9/02976

Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

公开(公告)号：US20230378275A1

公开(公告)日：2023-11-23

申请号：US17844746

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/205 ,  H01L29/7786

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.

公开(公告)号：US20230352557A1

公开(公告)日：2023-11-02

申请号：US17833885

申请日：2022-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L29/66 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/423 ,  H01L29/778 ,  H01L21/265 ,  H01L29/40

CPC classification number: H01L29/66462 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/42316 ,  H01L29/7786 ,  H01L21/26546 ,  H01L29/401

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A passivation layer is formed on the III-V compound barrier layer. A silicon layer is formed on the passivation layer, the III-V compound barrier layer, and the III-V compound semiconductor layer. A silicon implantation process is performed to the III-V compound semiconductor layer for forming a source doped region and a drain doped region in the III-V compound semiconductor layer under the silicon layer. A source electrode and a drain electrode are formed on the silicon layer. A source silicide layer is formed between the source electrode and the source doped region, and a drain silicide layer is formed between the drain electrode and the drain doped region. The source silicide layer and the drain silicide layer are partly formed on the passivation layer.

公开(公告)号：US20230329003A1

公开(公告)日：2023-10-12

申请号：US18209469

申请日：2023-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US20230320229A1

公开(公告)日：2023-10-05

申请号：US18195383

申请日：2023-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US11778922B2

公开(公告)日：2023-10-03

申请号：US17533003

申请日：2021-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

CPC classification number: H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

公开(公告)号：US20230200088A1

公开(公告)日：2023-06-22

申请号：US18113070

申请日：2023-02-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H10B61/00 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01F41/34 ,  G11C11/161 ,  H01F10/3254 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness

公开(公告)号：US20220392850A1

公开(公告)日：2022-12-08

申请号：US17369936

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chin-Chia Yang ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/00 ,  H01L23/522 ,  H01L29/417 ,  H01L21/02

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

公开(公告)号：US20220238800A1

公开(公告)日：2022-07-28

申请号：US17180876

申请日：2021-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Da-Jun Lin ,  Chau-Chung Hou ,  Wei-Xin Gao

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

公开(公告)号：US20220238468A1

公开(公告)日：2022-07-28

申请号：US17159080

申请日：2021-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.