公开(公告)号：US20160225662A1

公开(公告)日：2016-08-04

申请号：US14612235

申请日：2015-02-02

Applicant: United Microelectronics Corp.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Feng-Yi Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Yi-Kuan Wu ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76816 ,  H01L21/76879

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the ILD layer and the gate structure; forming an opening in the dielectric layer and the ILD layer; forming an organic dielectric layer (ODL) on the dielectric layer and in the opening; removing part of the ODL; removing part of the dielectric layer for extending the opening; removing the remaining ODL; and forming a contact plug in the opening.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在ILD层和栅极结构上形成介电层; 在介电层和ILD层中形成开口; 在介质层和开口中形成有机介电层（ODL）; 去除部分ODL; 去除用于延伸开口的电介质层的一部分; 去除剩余的ODL; 并在开口中形成接触塞。

公开(公告)号：US20150357436A1

公开(公告)日：2015-12-10

申请号：US14324252

申请日：2014-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Yi-Wei Chen ,  Ssu-I Fu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Yen-Liang Wu ,  Man-Ling Lu

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; performing a first dry etching process to form a recess in the substrate adjacent to the gate structure; and performing a second dry etching process to expand the recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 执行第一干蚀刻工艺以在所述衬底中邻近所述栅极结构形成凹陷; 以及执行第二干蚀刻工艺以使凹部膨胀。

公开(公告)号：US11799012B2

公开(公告)日：2023-10-24

申请号：US17012088

申请日：2020-09-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/423 ,  H10B12/00 ,  H01L21/285

CPC classification number: H01L29/4941 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/3213 ,  H01L29/42372 ,  H10B12/05 ,  H10B12/482 ,  H01L21/28518 ,  H01L21/28556 ,  H10B12/30

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20220130839A1

公开(公告)日：2022-04-28

申请号：US17570345

申请日：2022-01-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Kai-Jiun Chang ,  Yi-An Huang ,  Tsun-Min Cheng

IPC: H01L27/108

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

公开(公告)号：US11239241B2

公开(公告)日：2022-02-01

申请号：US16583268

申请日：2019-09-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/108 ,  H01L21/768

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

公开(公告)号：US11088023B2

公开(公告)日：2021-08-10

申请号：US15927106

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Wei-Hsin Liu

IPC: H01L21/768 ,  H01L21/324 ,  H01L27/108 ,  H01L23/532 ,  H01L21/285

Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

公开(公告)号：US20200258889A1

公开(公告)日：2020-08-13

申请号：US16858729

申请日：2020-04-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Chun-Chieh Chiu

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/3215 ,  H01L23/532

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

公开(公告)号：US20200227269A1

公开(公告)日：2020-07-16

申请号：US16261578

申请日：2019-01-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Ta-Wei Chiu ,  Chia-Lung Chang ,  Po-Chun Chen ,  Hong-Yi Fang ,  Yi-Wei Chen

IPC: H01L21/3105 ,  H01L27/108 ,  H01L21/027 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.

公开(公告)号：US10685964B2

公开(公告)日：2020-06-16

申请号：US16028364

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US20200075397A1

公开(公告)日：2020-03-05

申请号：US16134982

申请日：2018-09-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Chun Chen ,  Hsuan-Tung Chu ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Yu-Cheng Tung ,  Chia-Lung Chang

IPC: H01L21/762 ,  H01L21/02

Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.