-
公开(公告)号：US08015451B2
公开(公告)日：2011-09-06
申请号：US12356191
申请日：2009-01-20
IPC分类号： G06F11/00
CPC分类号： H04L41/0654
摘要： Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.
摘要翻译： 控制从发送单元到接收单元的数据信道中的不可靠数据传输。 根据数据通道中的错误率，激活旁路模式或缓冲模式。 如果选择了旁路模式，则通过旁路线将数据分组从发送单元直接传送到接收单元。 数据包在数据传输后进行错误检查。 如果选择了缓冲模式，则经由错误检测和校正单元和缓冲器单元通过缓冲线将数据从发送单元传送到接收单元。 在数据传输期间检测和纠正错误。
-
公开(公告)号：US08001411B2
公开(公告)日：2011-08-16
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译： 一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟选通信号产生时钟域控制，使得操作在所选择的周期上重新启动; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。
-
33.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY 有权方法，系统和计算机程序产品，用于处理高速缓存中的错误，无需处理器核心恢复公开(公告)号：US20090204766A1
公开(公告)日：2009-08-13
申请号：US12029516
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译： 用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。 将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。 在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别 缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。 执行流水线从较高级别的存储位置访问所请求的数据的副本。
-
公开(公告)号：US06681313B1
公开(公告)日：2004-01-20
申请号：US09566319
申请日：2000-05-08
IPC分类号： G06F1208
CPC分类号： G06F12/1027
摘要： In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to tables entries in which the entries are addressed after adding a plurality of address parts wherein the plurality is two (2) or (3). Particularly, a smaller and/or faster adder is used having, for example, only n=2 ports in the time critical path. In order to make the exact address calculation, during array accesses, a multiplexor is implemented to decide, after the TLB arrays are accessed for preselection, which of a plurality of possible entries has to be taken.
摘要翻译： 在用于在虚拟存储器系统中进行虚拟地址转换并实现诸如翻译后备缓冲器之类的表的系统中，能够更快地访问在其中条目被寻址的表条目的系统和方法，其中添加了多个地址部分，其中多个 是二（2）或（3）。 特别地，使用较小和/或更快的加法器，其具有例如在时间关键路径中仅n = 2个端口。 为了进行精确的地址计算，在阵列访问期间，实现多路复用器以在对预选择的TLB阵列进行访问之后决定必须采取多个可能的条目中的哪一个。
-
35.发明授权
公开(公告)号：US5974543A
公开(公告)日：1999-10-26
申请号：US24691
申请日：1998-02-17
申请人： Rolf Hilgendorf , Oliver Laub , Hans-Werner Tast
发明人： Rolf Hilgendorf , Oliver Laub , Hans-Werner Tast
IPC分类号： G06F9/38 , G06F9/42 , G06F12/0875 , G06F9/32
CPC分类号： G06F9/3806 , G06F12/0875 , G06F9/4426
摘要： An apparatus and a method for performing subroutine call and return operations in a computer having a processor with an instruction prefetch mechanism which includes a branch history table for storing target addresses of a plurality of branch instructions found in an instruction stream. The branch history table 22 contains a potential call instruction tag 37 and a return instruction tag 39. For each potential subroutine call instruction found in a prefetch instruction stream an address pair containing the call target address and the next sequential instruction address of the instruction is stored in a return identification stack 24. Subsequently detected branch instructions initiate an associative search on the next sequential instruction part in the return identification stack where a matching entry identifies the branch instruction as a return instruction. The address pair contained in the matching entry is then transferred to a return cache 30 which is arranged in parallel to the branch history table. The branch history table and the return cache are simultaneously accessed in the same operation cycle with the address 28 of each prefetched instruction, and if by the access a return instruction tag is found, the next sequential instruction address from the return cache is used as return address. A return cache update 32 is performed in response to a branch instruction in the instruction stream by a lookup of the return cache for an entry having a corresponding target address and by replacing the next sequential instruction address in said entry by the next sequential address of said branch instruction.
摘要翻译： 一种在具有具有指令预取机制的处理器的计算机中执行子程序调用和返回操作的装置和方法，该指令预取机制包括用于存储在指令流中发现的多个分支指令的目标地址的分支历史表。 分支历史表22包含潜在的呼叫指令标签37和返回指令标签39.对于在预取指令流中发现的每个潜在的子程序调用指令，存储包含该指令的调用目标地址和下一个顺序指令地址的地址对 随后检测到的分支指令在返回识别堆栈中的下一个顺序指令部分发起关联搜索，其中匹配条目将转移指令标识为返回指令。 然后将包含在匹配条目中的地址对传送到与分支历史表并行布置的返回高速缓存30。 分支历史表和返回缓存在与每个预取指令的地址28相同的操作周期中同时访问，并且如果通过访问返回指令标记被找到，则来自返回高速缓存的下一个顺序指令地址被用作返回 地址。 通过对具有相应目标地址的条目的返回高速缓存的查找来响应于指令流中的分支指令来执行返回高速缓存更新32，并且通过将所述条目中的下一个顺序指令地址替换为所述条目的下一个顺序地址， 分支指令。
-
36.发明授权Bus with request-dependent matching of the bandwidth available in both directions 失效具有与双向可用带宽的请求相关匹配的总线
公开(公告)号：US5872944A
公开(公告)日：1999-02-16
申请号：US712033
申请日：1996-09-11
CPC分类号： G06F13/4243
摘要： A method for improved use of bandwidth on a bus. A bus, such as a processor bus between a processor and an L2 cache, is established having two states: a first state in which one half of the bus allows transmission in one direction and the other half allows transmission in the opposite direction; and a second state in which the entire bus bandwidth comprising both bus halves allow transmission in one direction. To achieve this bus design, means are provided for selectively switching at least one of the bus halves' transmission directions.
摘要翻译： 一种改善总线带宽使用的方法。 建立了诸如处理器和L2高速缓存之间的处理器总线的总线，其具有两种状态：其中一半总线允许在一个方向上传输并且另一半允许在相反方向传输的第一状态; 并且第二状态，其中包括两个总线半部的整个总线带宽允许在一个方向上传输。 为了实现这种总线设计，提供了用于选择性地切换总线半部的传输方向中的至少一个的装置。
-
公开(公告)号：US09075732B2
公开(公告)日：2015-07-07
申请号：US13159590
申请日：2011-06-14
CPC分类号： G06F12/0897 , G06F12/12 , G06F2212/507
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
摘要翻译： 数据缓存用于包括较低级高速缓冲存储器和较高级缓存的计算机系统。 较高的缓存存储器接收提取请求。 然后由更高的缓存存储器确定要被替换的条目的状态。 如果接下来被替换的条目的状态指示该条目是专门拥有或修改的，则下一个被替换的条目的状态被改变，使得如果处理的访问与处理的访问相比，以更高的速度处理以下高速缓存访问 国家将保持不变。
-
公开(公告)号：US08856444B2
公开(公告)日：2014-10-07
申请号：US13459121
申请日：2012-04-28
CPC分类号： G06F12/0897 , G06F12/12 , G06F2212/507
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
摘要翻译： 数据缓存用于包括较低级高速缓冲存储器和较高级缓存的计算机系统。 较高的缓存存储器接收提取请求。 然后由更高的缓存存储器确定要被替换的条目的状态。 如果接下来被替换的条目的状态指示该条目是专门拥有或修改的，则下一个被替换的条目的状态被改变，使得如果处理的访问与处理的访问相比，以更高的速度处理以下高速缓存访问 国家将保持不变。
-
公开(公告)号：US08302043B2
公开(公告)日：2012-10-30
申请号：US12876319
申请日：2010-09-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.
摘要翻译： 公开了一种使用动态时钟门控验证逻辑电路设计的方法和系统。 所述方法包括：选择至少一个主粒子以将初始值确定为所述逻辑电路的初始化和/或所述逻辑电路的至少一个接口的刺激数据，为每个所选择的主子选择至少两个不同的动态时钟选通配置，执行 通过使用基于对应的主子种的所述确定的初始化和/或刺激数据，针对每个所选择的动态时钟门控配置，利用所述逻辑电路进行功能仿真，将与所述逻辑电路执行的功能模拟的仿真结果相互比较，用于至少两个不同的 所选择的动态时钟门控配置，并且如果至少两个模拟结果不相同，则报告错误。
-
公开(公告)号：US20110307666A1
公开(公告)日：2011-12-15
申请号：US13159590
申请日：2011-06-14
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F12/12 , G06F2212/507
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
摘要翻译： 数据缓存用于包括较低级高速缓冲存储器和较高级缓存的计算机系统。 较高的缓存存储器接收提取请求。 然后由更高的缓存存储器确定要被替换的条目的状态。 如果接下来被替换的条目的状态指示该条目是专门拥有或修改的，则下一个被替换的条目的状态被改变，使得如果处理的访问与处理的访问相比，以更高的速度处理以下高速缓存访问 国家将保持不变。
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.024 秒)
