公开(公告)号：US06432772B1

公开(公告)日：2002-08-13

申请号：US09682402

申请日：2001-08-30

申请人： King-Lung Wu ,  Kun-Chi Lin

发明人： King-Lung Wu ,  Kun-Chi Lin

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  H01L21/28525 ,  H01L28/75 ,  H01L28/91 ,  Y10S438/964

摘要： An isolation layer is formed on a substrate of a semiconductor wafer. At least one recess is formed in the isolation layer by way of a photo-etching-process. A two stage in-situ doped deposition process is then performed to form a first doped amorphous silicon (&agr;-Si) layer and a second doped amorphous silicon (&agr;-Si) layer doping concentration of the second doped amorphous silicon (&agr;-Si) layer being less than that of the first doped amorphous silicon layer. A dielectric layer is formed to fill the recess, and a planarization process removes portions of the second doped amorphous silicon layer, the first doped amorphous silicon layer and the dielectric layer on the surface of the isolation layer. Finally, the dielectric layer and the isolation layer are removed, and a hemi-spherical grain (HSG) process is performed to form a rough surface with a plurality of hemi-spherical grains on the surface of the second doped amorphous silicon layer.

摘要翻译： 在半导体晶片的基板上形成隔离层。 通过光蚀刻工艺在隔离层中形成至少一个凹部。 然后进行两级原位掺杂沉积工艺以形成第二掺杂非晶硅（α-Si）层和第二掺杂非晶硅（α-Si）层掺杂浓度的第二掺杂非晶硅（α-Si） 层小于第一掺杂非晶硅层的层。 形成介电层以填充凹部，并且平坦化处理去除隔离层表面上的第二掺杂非晶硅层，第一掺杂非晶硅层和电介质层的部分。 最后，去除电介质层和隔离层，并且在第二掺杂非晶硅层的表面上执行半球形晶粒（HSG）工艺以形成具有多个半球形晶粒的粗糙表面。

公开(公告)号：US06429135B1

公开(公告)日：2002-08-06

申请号：US09754354

申请日：2001-01-05

申请人： Horng-Nan Chern ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Kun-Chi Lin

IPC分类号： H01L21302

CPC分类号： H01L21/823425 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823468

摘要： The semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. Firstly, a dielectric layer is formed on the semiconductor wafer to cover the gate. An etching back process is then performed to remove portions of both the dielectric layer and the silicon oxide spacer. Finally, a silicon nitride spacer is formed on the dielectric layer around the cap layer. The silicon nitride spacer is positioned on the surface of the dielectric layer and functions in reducing stress between the silicon nitride spacer and the substrate.

摘要翻译： 半导体晶片包括衬底，位于衬底上的栅极，位于栅极顶部的覆盖层和位于栅极和盖层两侧的氧化硅间隔物。 首先，在半导体晶片上形成介电层以覆盖栅极。 然后进行蚀刻反应处理以去除电介质层和氧化硅间隔物的部分。 最后，在覆盖层周围的电介质层上形成氮化硅间隔物。 氮化硅间隔物定位在电介质层的表面上，起减少氮化硅间隔物和衬底之间的应力的作用。

公开(公告)号：US06365454B1

公开(公告)日：2002-04-02

申请号：US09742465

申请日：2000-12-20

申请人： Tzung-Han Lee ,  Alex Hou ,  Kun-Chi Lin

发明人： Tzung-Han Lee ,  Alex Hou ,  Kun-Chi Lin

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/91

摘要： A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate. Finally, conductive material is deposited into the node contact openings and the cylindrical openings to become the lower electrodes and the node contacts respectively.

公开(公告)号：US06329244B1

公开(公告)日：2001-12-11

申请号：US09734838

申请日：2000-12-11

申请人： King-Lung Wu ,  Kun-Chi Lin

发明人： King-Lung Wu ,  Kun-Chi Lin

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L28/92

摘要： A method of manufacturing a dynamic random access memory cell. A substrate having a transistor therein is provided. A first dielectric layer is formed over the substrate and the transistor. A bit line having a cap layer thereon is formed over the first dielectric layer. A protective layer is formed over the substrate covering the bit line. A second dielectric layer is formed over the protective layer. The second dielectric layer is etched in a self-aligned process. The etching continues penetrating the protective layer and the first dielectric layer until the substrate is exposed so that a node contact opening and an opening for forming the lower electrode of a capacitor are formed at the same time. Thereafter, polysilicon material is deposited into the node contact opening and the lower electrode opening to form a polysilicon layer. The upper surface of the polysilicon layer is slightly below the lower electrode opening. A spacer is formed on the sidewalls of the lower electrode opening above the polysilicon layer. Using the spacers as a mask, the polysilicon layer is etched to form a lower electrode with a recess groove above the node contact opening. The second dielectric layer and the spacers are removed. To complete the fabrication of the DRAM cell capacitor, a dielectric layer is formed over the lower electrode and an upper electrode is formed over the dielectric layer.

摘要翻译： 一种制造动态随机存取存储单元的方法。 提供其中具有晶体管的衬底。 在衬底和晶体管上形成第一介电层。 其上具有盖层的位线形成在第一介电层上。 在覆盖位线的基板上形成保护层。 在保护层上形成第二电介质层。 在自对准工艺中蚀刻第二介电层。 蚀刻继续穿透保护层和第一介电层，直到基板被暴露，从而同时形成用于形成电容器的下电极的节点接触开口和开口。 此后，多晶硅材料沉积到节点接触开口和下电极开口中以形成多晶硅层。 多晶硅层的上表面略低于下电极开口。 在多晶硅层上方的下电极开口的侧壁上形成间隔物。 使用间隔物作为掩模，蚀刻多晶硅层以形成具有在节点接触开口上方的凹槽的下电极。 去除第二电介质层和间隔物。 为了完成DRAM单元电容器的制造，在下电极上形成电介质层，并且在电介质层上形成上电极。

公开(公告)号：US06255229B1

公开(公告)日：2001-07-03

申请号：US09074780

申请日：1998-05-08

申请人： Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

发明人： Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

IPC分类号： H01L21469

CPC分类号： H01L21/0214 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31625 ,  H01L21/76801

摘要： A method for forming a semiconductor dielectric layer comprising the steps of providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first dielectric layer, and finally a second dielectric layer is formed over the silicon oxy-nitride layer.

摘要翻译： 一种形成半导体电介质层的方法，包括以下步骤：提供其上已经形成有多个半导体器件的衬底，然后在衬底上形成第一电介质层。 接下来，在第一介电层上形成氮氧化硅层，最后在氮氧化硅层上形成第二电介质层。

公开(公告)号：US06218271B1

公开(公告)日：2001-04-17

申请号：US09414901

申请日：1999-10-08

申请人： Tzung-Han Lee ,  Kun-Chi Lin

发明人： Tzung-Han Lee ,  Kun-Chi Lin

IPC分类号： H01L213205

CPC分类号： H01L21/76895 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76897 ,  H01L28/40

摘要： This invention provides a method of forming a landing pad on the drain and source of a MOS transistor. The MOS transistor is formed on a silicon substrate of a semiconductor wafer and comprises a gate on the silicon substrate with a spacer around its periphery portion, a drain and a source on the surface of the silicon substrate and on opposite sides of the gate. The method comprises forming a conductive layer of uniform thickness above the drain or source of the MOS transistor. The conductive layer is used as the landing pads for the drain or source. The height of the conductive layer is lower than that of the spacer surrounding the gate so that the spacer electrically isolates the gate and the conductive layer.

摘要翻译： 本发明提供一种在MOS晶体管的漏极和源极上形成层叠焊盘的方法。 MOS晶体管形成在半导体晶片的硅衬底上，并且在硅衬底上具有围绕其周边部分的隔离物的栅极，在硅衬底的表面上的漏极和源极以及栅极的相对侧上。 该方法包括在MOS晶体管的漏极或源极之上形成均匀厚度的导电层。 导电层用作漏极或源极的着陆焊盘。 导电层的高度低于围绕栅极的间隔物的高度，使得间隔物电隔离栅极和导电层。

公开(公告)号：US06188116B1

公开(公告)日：2001-02-13

申请号：US09172381

申请日：1998-10-14

申请人： Kun-Chi Lin

发明人： Kun-Chi Lin

IPC分类号： H01L2701

CPC分类号： H01L27/10888 ,  H01L21/3205 ,  H01L21/32053 ,  H01L21/76877 ,  H01L27/10885

摘要： A structure of a polysilicon via that includes a semiconductor substrate, a conducting layer on the substrate, a dielectric layer on the conducting layer, a polysilicon plug formed in the dielectric layer, a polysilicon layer on the polysilicon plug, and a silicide layer formed on the polysilicon layer. The polysilicon layer is electrically connected to the conducting layer through the polysilicon plug. The structure of a polysilicon via according to the invention prevents the occurrence of leakage currents in the presence of misalignment in the follow-up photolithography process.

摘要翻译： 多晶硅通孔的结构，其包括半导体衬底，衬底上的导电层，导电层上的电介质层，形成在电介质层中的多晶硅插塞，多晶硅插塞上的多晶硅层，以及形成在多晶硅层上的硅化物层 多晶硅层。 多晶硅层通过多晶硅插塞电连接到导电层。 根据本发明的多晶硅通孔的结构防止在后续光刻工艺中存在未对准的情况下发生漏电流。

公开(公告)号：US6162678A

公开(公告)日：2000-12-19

申请号：US188916

申请日：1998-11-09

申请人： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

发明人： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

IPC分类号： H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/76885 ,  H01L21/76888 ,  H01L27/10885

摘要： A method for fabricating a type of bit line is able to form a small-sized bit line. In this method a first dielectric layer, a first conductive layer, and a second conductive layer are formed on a substrate in sequence. The first dielectric layer is exposed, then a second conducting wire and a first conducting wire are formed, respectively. A portion of the second conducting wire is removed by a cleaning liquid, so that the feature size of the second conducting wire is less than the feature size of the first conducting wire. An oxide layer is formed on the second conducting wire and the first conducting wire by performing a thermal treatment. The feature size of the second conducting wire is approximately equal to the feature size of the first conducting wire.

摘要翻译： 一种用于制造位线的方法能够形成小尺寸的位线。 在该方法中，依次在基板上形成第一电介质层，第一导电层和第二导电层。 第一介质层被暴露，然后分别形成第二导线和第一导线。 第二导线的一部分被清洁液体除去，使得第二导线的特征尺寸小于第一导线的特征尺寸。 通过进行热处理，在第二导线和第一导线上形成氧化物层。 第二导线的特征尺寸近似等于第一导线的特征尺寸。

公开(公告)号：US6140202A

公开(公告)日：2000-10-31

申请号：US208739

申请日：1998-12-08

申请人： Horng-Nan Chern ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Kun-Chi Lin

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/8242

CPC分类号： H01L28/92 ,  H01L21/32139 ,  H01L27/10852

摘要： A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

摘要翻译： 提供一种制造双缸电容器的方法。 双缸电容器具有具有双重同心圆筒结构的存储电极。 电介质层和顶电极依次形成在底电极上。 因此，通过本发明的双缸电容器来扩大存储区域。 因此，可以有效地增加电容器的电容。

公开(公告)号：US6100014A

公开(公告)日：2000-08-08

申请号：US199883

申请日：1998-11-24

申请人： Benjamin Szu-Min Lin ,  Kun-Chi Lin

发明人： Benjamin Szu-Min Lin ,  Kun-Chi Lin

IPC分类号： G03F7/40 ,  G03F7/00

CPC分类号： G03F7/405 ,  G03F7/40

摘要： A semiconductor fabrication method is provided for forming an opening in a dielectric layer, which can help downsize the critical dimension of the resulting opening through the use of a photoresist layer with silylated sidewall spacers. By this method, the first step is to coat a base photoresist layer over the dielectric layer. Next, a photolithographic process is performed to remove a selected part of the base photoresist layer. Then, a conformational coating process is performed to coat a silylatable photoresist layer over the base photoresist layer to a controlled predefined thickness. Subsequently, a silylation process is performed on the silylatable photoresist layer so as to form a silylated photoresist layer over all the exposed surfaces of the base photoresist layer. After this, a first etching process is performed on the silylated photoresist layer, with the remaining portions of the silylated photoresist layer serving as silylated sidewall spacers on the base photoresist layer. Then, with the combined structure of the base photoresist layer and the overlying silylated sidewall spacers serving as mask, a second etching process is performed on the dielectric layer to etch away the unmasked part of the dielectric layer to form the intended opening in the dielectric layer.

摘要翻译： 提供半导体制造方法用于在电介质层中形成开口，这有助于通过使用具有甲硅烷化侧壁间隔物的光致抗蚀剂层来减小所得开口的临界尺寸。 通过该方法，第一步是在介电层上涂覆基底光致抗蚀剂层。 接下来，进行光刻工艺以去除基底光致抗蚀剂层的选定部分。 然后，进行构象涂覆工艺以将基础光致抗蚀剂层上的可甲硅烷化的光致抗蚀剂层涂覆到受控的预定厚度。 随后，对可甲硅烷化的光致抗蚀剂层进行甲硅烷基化处理，以在基底光致抗蚀剂层的所有暴露表面上形成甲硅烷基化的光致抗蚀剂层。 之后，对甲硅烷基化的光致抗蚀剂层进行第一蚀刻工艺，其中甲基化光致抗蚀剂层的其余部分用作基底光致抗蚀剂层上的甲硅烷基化侧壁间隔物。 然后，利用基底光致抗蚀剂层和上覆的甲硅烷基化侧壁间隔物用作掩模的组合结构，对电介质层进行第二蚀刻工艺，以蚀刻掉电介质层的未屏蔽部分以在电介质层中形成预期的开口 。