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公开(公告)号：US09779830B2
公开(公告)日：2017-10-03
申请号：US15233231
申请日：2016-08-10
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/3445 , G11C16/0483 , G11C16/14 , G11C16/3472
Abstract: Provided is an erase method for a non-volatile semiconductor memory device to compensate for the change in property of a memory cell, in proportion to the number of data rewrites to the memory cell. The erase method has an erase step to erase charges of a charge accumulation layer by applying an erase voltage to a channel region of a selected memory cell, and a soft-programming step to perform soft-programming to the charges in the accumulation layer by virtue of applying a soft-programming voltage which is smaller than a programming voltage to program the memory cell. The erase voltage is increased step by step when it is applied repeatedly. The soft-programming voltage is decreased step by step when it is applied repeatedly.
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公开(公告)号：US09514826B2
公开(公告)日：2016-12-06
申请号：US14926420
申请日：2015-10-29
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: The invention provides a programming method for a NAND-type flash memory capable of reducing the drop in reliability due to data-rewriting. The programming method includes: when a block program mode is executed to perform programming for a plurality of pages in a block, while the data to be programmed is being loaded into a cache memory; and erasing the selected block; and programming the data to be programmed which is loaded into the cache memory to the erased block.
Abstract translation: 本发明提供了一种NAND型闪存的编程方法，能够减少由于数据重写导致的可靠性下降。 编程方法包括：当块被编程的数据被加载到高速缓冲存储器中时，执行块编程模式以对块中的多个页执行编程; 并擦除所选择的块; 并将要编程的数据编程到缓存存储器中以被擦除的块。
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公开(公告)号：US09317053B2
公开(公告)日：2016-04-19
申请号：US14263536
申请日：2014-04-28
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Hiroki Murakami
IPC: H01L29/8605 , H01L27/08 , G05F1/575 , H01L49/02
CPC classification number: G05F1/575 , H01L27/0802 , H01L28/20
Abstract: The invention provides a voltage regulator. The voltage regulator (100) of the invention includes a comparison circuit (20) and a voltage divider circuit (110). The voltage divider circuit (110) has a PMOS transistor (T6) connected to a voltage source (VDD) and resistors (R1, R2, R3, R4, R5 and R6) serially connected between the transistor (T6) and a reference voltage. A feedback voltage generated from a node (N3) between resistors R4 and R5 is provided to the comparison circuit (20). In addition, a middle voltage (Vm) generated from a node (Nc) of the resistors is provided to a well region, so the parasitic capacitance is reduced.
Abstract translation: 本发明提供一种电压调节器。 本发明的电压调节器（100）包括比较电路（20）和分压电路（110）。 分压器电路（110）具有连接到电压源（VDD）的PMOS晶体管（T6）和串联连接在晶体管（T6）和参考电压之间的电阻器（R1，R2，R3，R4，R5和R6）。 从电阻器R4和R5之间的节点（N3）产生的反馈电压被提供给比较电路（20）。 此外，从电阻器的节点（Nc）产生的中间电压（Vm）被提供给阱区域，因此寄生电容减小。
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公开(公告)号：US09183934B2
公开(公告)日：2015-11-10
申请号：US13744965
申请日：2013-01-18
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C2216/18
Abstract: A flash memory capable of writing or deleting a split block is provided. A flash memory includes a memory array comprising a plurality of blocks, and a word line selection circuit, wherein each of the plurality of blocks is formed by a plurality of cell units in a well. The cell unit comprises N memory cells, a selection transistor coupled to one terminal of the memory cells, a selection transistor coupled to the other terminal of the memory cells, and a dummy selection transistor coupled between the memory cells. The word line selection circuit splits the block into a first block and a second block to use according to the operation of data writing or data deleting.
Abstract translation: 提供了能够写入或删除分割块的闪速存储器。 闪速存储器包括包括多个块的存储器阵列和字线选择电路，其中多个块中的每一个由阱中的多个单元单元形成。 单元单元包括N个存储单元，耦合到存储单元的一个端子的选择晶体管，耦合到存储单元的另一个端子的选择晶体管，以及耦合在存储单元之间的虚拟选择晶体管。 字线选择电路根据数据写入或数据删除的操作将块分割成第一块和第二块。
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公开(公告)号：US09070460B2
公开(公告)日：2015-06-30
申请号：US14027926
申请日：2013-09-16
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/16 , G11C16/10 , G11C16/3454
Abstract: A non-volatile semiconductor memory includes a memory array. In a programming operation, programming pulses are applied to a page of the memory array to program data to the page. In an erase operation, erase pulses are applied to a block of the memory array to erase data in the block. The non-volatile semiconductor memory performs a pre-program operation before the erase operation and a post-erase operation after the erase operation. In the pre-program operation, each page of the block is programmed according to voltage information relating programming pulses. In the erase operation, data in the block is erased according to the voltage information relating programming pulses.
Abstract translation: 非易失性半导体存储器包括存储器阵列。 在编程操作中，将编程脉冲施加到存储器阵列的页面以将数据编程到页面。 在擦除操作中，擦除脉冲被施加到存储器阵列的块以擦除块中的数据。 非易失性半导体存储器在擦除操作之前进行预编程操作，并且在擦除操作之后执行擦除后操作。 在预编程操作中，根据与编程脉冲相关的电压信息对块的每一页进行编程。 在擦除操作中，根据与编程脉冲相关的电压信息擦除块中的数据。
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Patent Agency Ranking
公开(公告)号：US12198745B2
公开(公告)日：2025-01-14
申请号：US17736995
申请日：2022-05-04
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
IPC: G11C11/00
Abstract: A semiconductor storage device and its writing method are provided. A memory cell array is formed on a substrate, and the memory cell array has an NOR array with an NOR flash memory structure and a resistive random access array with a resistive random access memory (RRAM) structure. A read/write control unit charges a selected global bit line when a set write operation is performed on a selected memory cell of the resistive random access array, and a set write voltage is applied to the selected memory cell by applying a voltage charging the selected global bit line.
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公开(公告)号：US20230253051A1
公开(公告)日：2023-08-10
申请号：US18080752
申请日：2022-12-14
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/102 , G11C16/26 , G11C16/3459 , G11C16/08
Abstract: The disclosure provides a semiconductor device and a programming method capable of programming with reduced power consumption. The programming method of the NAND flash memory of the disclosure prepares high-speed programming blocks and copy back block for final data storage, responding to an external input programming command while in an power-saving mode, program 1/2 pages of data in even-numbered pages and odd-numbered pages of the high-speed programming blocks respectively, then the data is read out from the high-speed programming blocks, and the read data is normally programmed into the copy back block.
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公开(公告)号：US11683935B2
公开(公告)日：2023-06-20
申请号：US16111237
申请日：2018-08-24
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
IPC: G11C16/04 , H10B43/27 , H10B41/00 , H10B43/30 , H10B43/35 , H10B43/50 , G11C16/06 , G11C11/56 , G11C16/10
CPC classification number: H10B43/27 , G11C16/0466 , H10B41/00 , H10B43/30 , H10B43/35 , H10B43/50 , G11C11/5671 , G11C16/06 , G11C16/10
Abstract: A NOR flash memory comprising a memory cell having a three-dimensional structure for saving power consumption is provided. The flash memory of the present invention includes a pillar part, a charge accumulating part, an insulating part, a control gate and a selecting gate. The pillar part extends in a vertical direction from a surface of a substrate and includes a conductive semiconductor material. The charge accumulating part is formed by surrounding the pillar part. The insulating part is formed by surrounding the pillar part. The control gate is formed by surrounding the charge accumulating part. The selecting gate is formed by surrounding the insulating part. One end of the pillar part is electrically connected to a bit line via a contact hole and another one end of the pillar part is electrically connected to a conductive region formed on the surface of the substrate.
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公开(公告)号：US20230170021A1
公开(公告)日：2023-06-01
申请号：US17975609
申请日：2022-10-28
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0038 , G11C13/0026
Abstract: A semiconductor memory device capable of automatically restoring writing interrupted due to a momentary stop or a fluctuation of a power supply voltage is provided. A non-volatile memory of the disclosure includes a memory cell array formed with a NOR array and a variable resistance array. When the power supply voltage drops to a power-off level during writing into the NOR array, a reading/writing control unit writes unwritten data into the variable resistance array. Subsequently, when a power-on of the power supply voltage is detected, the reading/writing control unit reads the unwritten data from the variable resistance array and writes the unwritten data into the NOR array, so that interrupted writing is restored.
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公开(公告)号：US20220036947A1
公开(公告)日：2022-02-03
申请号：US17367651
申请日：2021-07-06
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
IPC: G11C13/00
Abstract: An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.
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