公开(公告)号：US10354733B1

公开(公告)日：2019-07-16

申请号：US15786321

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Elliott Delaye ,  Ashish Sirasao ,  Yongjun Wu ,  Aaron Ng

IPC: G11C8/00 ,  G11C16/10 ,  G06N3/04 ,  G06F12/06 ,  G06F13/16 ,  G06N20/00

Abstract: Methods and apparatus are described for partitioning and reordering block-based matrix multiplications for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). By preloading and hierarchically caching the blocks, examples of the present disclosure reduce the double data rate (DDR) memory intake bandwidth for software-defined GEMM accelerators.

公开(公告)号：US10303833B1

公开(公告)日：2019-05-28

申请号：US15429014

申请日：2017-02-09

Applicant: Xilinx, Inc.

Inventor： Aman Gayasen ,  Surya Pratik Saha ,  Elliott Delaye ,  Shangzhi Sun ,  Ashish Sirasao

IPC: G06F17/50

Abstract: Parallelizing operations for implementing a circuit design can include dividing, using a processor, the circuit design into a plurality of partitions, wherein each partition is stored as a separate file, for each partition, generating, using the processor, a timing arc file specifying boundary delays for the partition, and generating, using the processor, a partition design file specifying interfaces of the partitions. Using the processor, a plurality of processes executing in parallel can be initiated. Each process is adapted to operate on a selected partition using the partition design file and the timing arc files for the other partitions to generate an updated file for the selected partition.

公开(公告)号：US10289786B1

公开(公告)日：2019-05-14

申请号：US15634016

申请日：2017-06-27

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Shangzhi Sun ,  Ashish Sirasao ,  Nithin Kumar Guggilla

IPC: G06F17/50

Abstract: Reducing latency of a circuit design can include determining, using a processor, a set of sequential circuit elements of a circuit design that meets a condition for removal from the circuit design, wherein the condition is dependent upon a target technology process and a target operating frequency. Using the processor, a feasible cut for a selected sequential circuit element of the set is determined. The selected sequential circuit element and each other sequential circuit element of the set that is part of the cut is removed from the circuit design using the processor.

公开(公告)号：US09460253B1

公开(公告)日：2016-10-04

申请号：US14482945

申请日：2014-09-10

Applicant: Xilinx, Inc.

Inventor： Elliott Delaye ,  Ashish Sirasao ,  Krishna Garlapati ,  Bing Tian

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F2217/14 ,  G06F2217/64 ,  G06F2217/66

Abstract: In an example, a method of processing a circuit design includes: determining a first partition in a description of the circuit design having a hierarchy of design objects, the first partition including at least one design object in the hierarchy of design objects; generating a signature for the first partition; querying a database with the signature of the first partition to identify a plurality of predefined implementations of the first partition; and generating an implementation of the circuit design for a target integrated circuit (IC) based on a selected predefined implementation of the plurality of predefined implementations for the first partition.

Abstract translation: 在一个示例中，一种处理电路设计的方法包括：在具有设计对象层级的电路设计的描述中确定第一分区，第一分区包括设计对象层级中的至少一个设计对象; 生成第一分区的签名; 用第一分区的签名查询数据库以识别第一分区的多个预定义的实现; 以及基于用于所述第一分区的所述多个预定义实现的所选择的预定义实现来生成用于目标集成电路（IC）的电路设计的实现。

公开(公告)号：US08938700B1

公开(公告)日：2015-01-20

申请号：US13762251

申请日：2013-02-07

Applicant: Xilinx, Inc.

Inventor： Elliott Delaye ,  Alireza S. Kaviani ,  Ashish Sirasao ,  Yinyi Wang

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Data-driven processing of a circuit design includes converting each pattern of one or more input patterns from a first format into a second format. Each pattern identifies one or more inputs and one or more outputs and specifies each function that generates each of the one or more outputs from the one or more inputs. Each pattern of the second format is stored in a database. An input circuit design is searched for circuit design elements that match patterns in the database. Data indicative of each pattern in the database that matches a circuit design element is output.

Abstract translation: 电路设计的数据驱动处理包括将一个或多个输入模式的每个模式从第一格式转换为第二格式。 每个模式识别一个或多个输入和一个或多个输出，并且指定从一个或多个输入产生一个或多个输出中的每一个的每个功能。 第二格式的每个模式都存储在数据库中。 搜索与数据库中的模式匹配的电路设计元素的输入电路设计。 输出指示数据库中与电路设计元素匹配的每个模式的数据。

公开(公告)号：US08667436B1

公开(公告)日：2014-03-04

申请号：US13782123

申请日：2013-03-01

Applicant: Xilinx, Inc.

Inventor： Krishna Garlapati ,  Elliot Delaye ,  Ashish Sirasao

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022 ,  G06F17/5045

Abstract: The disclosure describes approaches for processing a circuit design. For each object of a plurality of objects of the circuit design, a respective key is generated as a function of a plurality of configuration parameter values of the object. Each object is renamed with a unique name that includes the key. A netlist of the circuit design is generated using the unique names and keys of the objects.

Abstract translation: 本公开描述了用于处理电路设计的方法。 对于电路设计的多个对象的每个对象，根据对象的多个配置参数值生成相应的键。 每个对象都使用包含密钥的唯一名称进行重命名。 使用对象的唯一名称和密钥生成电路设计的网表。

公开(公告)号：US12086572B1

公开(公告)日：2024-09-10

申请号：US15786452

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Yongjun Wu ,  Jindrich Zejda ,  Elliott Delaye ,  Ashish Sirasao

IPC: G06F8/30 ,  G06F8/41 ,  G06F12/06 ,  G06N3/04 ,  G06N20/00

CPC classification number: G06F8/313 ,  G06F8/47 ,  G06F12/0646 ,  G06N3/04 ,  G06N20/00

Abstract: Embodiments herein describe techniques for expressing the layers of a neural network in a software model. In one embodiment, the software model includes a class that describes the various functional blocks (e.g., convolution units, max-pooling units, rectified linear units (ReLU), and scaling functions) used to execute the neural network layers. In turn, other classes in the software model can describe the operation of each of the functional blocks. In addition, the software model can include conditional logic for expressing how the data flows between the functional blocks since different layers in the neural network can process the data differently. A compiler can convert the high-level code in the software model (e.g., C++) into a hardware description language (e.g., register transfer level (RTL)) which is used to configure a hardware system to implement a neural network accelerator.

公开(公告)号：US12061990B2

公开(公告)日：2024-08-13

申请号：US15786434

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Yongjun Wu ,  Jindrich Zejda ,  Elliott Delaye ,  Ashish Sirasao

IPC: G06N3/086 ,  G06F9/38 ,  G06N3/045 ,  G06N3/063 ,  G06N20/00 ,  H04W72/54

CPC classification number: G06N3/086 ,  G06F9/3844 ,  G06N3/063 ,  G06N20/00 ,  H04W72/54 ,  G06N3/045

Abstract: Embodiments herein describe techniques for static scheduling a neural network implemented in a massively parallel hardware system. The neural network may be scheduled using three different scheduling levels referred to herein as an upper level, an intermediate level, and a lower level. In one embodiment, the upper level includes a hardware or software model of the layers in the neural network that establishes a sequential order of functions that operate concurrently in the hardware system. In the intermediate level, identical processes in the functions defined in the upper level are connected to form a systolic array or mesh and balanced data flow channels are used to minimize latency. In the lower level, a compiler can assign the operations performed by the processing elements in the systolic array to different portions of the hardware system to provide a static schedule for the neural network.

公开(公告)号：US11694066B2

公开(公告)日：2023-07-04

申请号：US15785679

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Jindrich Zejda ,  Elliott Delaye ,  Xiao Teng ,  Sonal Santan ,  Soren T. Soe ,  Ashish Sirasao ,  Ehsan Ghasemi ,  Sean Settle

IPC: G06N3/063 ,  G06N3/10 ,  G06N3/08 ,  G06N3/04 ,  G06V10/94 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06N3/10 ,  G06N3/045 ,  G06V10/955

Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator using a library. The neural network application may execute on a host computing system while the neural network accelerator executes on a massively parallel hardware system, e.g., a FPGA. The library operates a pipeline for submitting the tasks received from the neural network application to the neural network accelerator. In one embodiment, the pipeline includes a pre-processing stage, an FPGA execution stage, and a post-processing stage which each correspond to different threads. When receiving a task from the neural network application, the library generates a packet that includes the information required for the different stages in the pipeline to perform the tasks. Because the stages correspond to different threads, the library can process multiple packets in parallel which can increase the utilization of the neural network accelerator on the hardware system.

公开(公告)号：US11188697B1

公开(公告)日：2021-11-30

申请号：US17141983

申请日：2021-01-05

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Rajeev Patwari ,  Nithin Kumar Guggilla ,  Ashish Sirasao ,  Krishna Garlapati

IPC: G06F30/333 ,  G06F30/343 ,  G06F30/3308 ,  G06F30/398 ,  G06F11/00 ,  G06F9/34 ,  G06F9/26 ,  G06F13/00 ,  G01R31/28 ,  G11C7/10 ,  G11C29/04 ,  G11B27/36 ,  G11B7/00 ,  G11B11/00 ,  H01L21/00 ,  G06F11/32 ,  G06F12/00

Abstract: Determining on-chip memory access patterns can include modifying a circuit design to include a profiler circuit for a random-access memory (RAM) of the circuit design, wherein the profiler circuit is configured to monitor an address bus of the RAM, and modifying the circuit design to include a debug circuit connected to the profiler circuit. Usage data for the RAM can be generated by detecting, using the profiler circuit, addresses of the RAM accessed during a test of the circuit design, as implemented in an integrated circuit. The usage data for the RAM can be output using the debug circuit.