公开(公告)号：US10673424B1

公开(公告)日：2020-06-02

申请号：US16388786

申请日：2019-04-18

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Christophe Erdmann

IPC: H03K5/13 ,  H03M1/08 ,  H03K5/00

Abstract: Apparatus and associated methods relating to a switch leakage compensation delay circuit include a compensating transistor configured to passively bypass a leakage current around a capacitor that connects in series with a control transistor. In an illustrative example, the capacitor and the compensating transistor may be connected in parallel between a first node and a second node. The compensating transistor gate may be tied, for example, directly to its source and to the second node. The control transistor may connect its drain to the second node. When a control signal turns off the control transistor, a leakage current of the control transistor may be supplied from a leakage current of the compensating transistor such that the voltage across the capacitor may be maintained substantially constant. The delay circuit may advantageously mitigate the capacitor's voltage droop to reduce clock time skew, for example, in low speed interleaved ADC operation.

公开(公告)号：US10476514B1

公开(公告)日：2019-11-12

申请号：US15992797

申请日：2018-05-30

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  John E. McGrath ,  Conrado K. Mesadri ,  Woon C. Wong ,  Ali Boumaalif ,  Christophe Erdmann ,  Brendan Farley

IPC: H03M1/12 ,  G01R31/3185 ,  H03M1/10 ,  H04L12/43 ,  H04L12/433

Abstract: An integrated circuit is described. The integrated circuit comprises a first portion having programmable resources; a second portion having hardened circuits including an analog-to-digital converter circuit configured to receive an input signal and generate an output signal; and a monitor circuit configured to receive an output signal generated by the analog-to-digital converter circuit; wherein the monitor circuit is configurable to control a calibration of the analog-to-digital converter circuit based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

公开(公告)号：US10371725B1

公开(公告)日：2019-08-06

申请号：US15994060

申请日：2018-05-31

Applicant: Xilinx, Inc.

Inventor： Alonso Morgado ,  Bruno Miguel Vaz ,  Edward Cullen ,  Christophe Erdmann

IPC: G08B21/00 ,  G01R19/165 ,  H02H9/04 ,  H03K19/003

Abstract: Examples of the present disclosure provide out-of-range voltage detection and protection in integrated circuits (ICs). In some examples, an IC includes an envelope detector, a comparator, and a switch. The envelope detector is configured to generate an envelope signal of a signal and output the envelope signal on an output node of the envelope detector. A first input node of the comparator is coupled to the output node of the envelope detector. The comparator is configured to compare respective signals provided on the first and second input nodes of the comparator and generate a comparison signal in response to the comparison. The comparator is further configured to output the comparison signal on the output node of the comparator. The switch is connected between a protected node and a protection node and is configured to be selectively opened or closed based, at least in part, on the comparison signal.

公开(公告)号：US09432036B1

公开(公告)日：2016-08-30

申请号：US14847405

申请日：2015-09-08

Applicant: Xilinx, Inc.

Inventor： Donnacha Lowney ,  Christophe Erdmann

IPC: H03M1/66 ,  H03M1/00 ,  H03K17/041 ,  H03K19/21 ,  H03M1/74

CPC classification number: H03M1/66 ,  H03K17/04106 ,  H03K19/21 ,  H03M1/742

Abstract: In one example, a current steering circuit for a digital-to-analog converter (DAC) includes a source-coupled transistor pair responsive to a differential gate voltage; a current source coupled to the source-coupled transistor pair operable to source a bias current; a load circuit coupled to the source-coupled transistor pair operable to provide a differential output voltage; a driver having a first input, a second input, and a differential output, the differential output providing the differential gate voltage; and combinatorial logic having a data input, a clock input, a true output, and a complement output, the true output and the complement output respectively coupled to the first input and the second input of the driver, the combinatorial logic operable to exclusively OR a data signal on the data input and a clock signal on the clock input.

Abstract translation: 在一个示例中，用于数模转换器（DAC）的电流转向电路包括响应于差分栅极电压的源极耦合晶体管对; 耦合到源极耦合晶体管对的电流源，可操作地源极偏置电流; 耦合到所述源极耦合晶体管对的负载电路，其可操作以提供差分输出电压; 具有第一输入，第二输入和差分输出的驱动器，所述差分输出提供所述差分栅极电压; 以及具有数据输入，时钟输入，真实输出和补码输出的组合逻辑，分别耦合到驱动器的第一输入和第二输入的真实输出和补码输出，组合逻辑可操作以专门地将或 数据输入上的数据信号和时钟输入的时钟信号。

公开(公告)号：US20140266824A1

公开(公告)日：2014-09-18

申请号：US13843909

申请日：2013-03-15

Applicant: XILINX, INC.

Inventor： Donnacha Lowney ,  Christophe Erdmann ,  Edward Cullen

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/742

Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.

Abstract translation: 公开了一种用于校准信号转换器的装置。 该装置包括第一数模转换器（“DAC”）和耦合到第一DAC的输出端口的校准系统。 校准系统包括第二DAC。 校准系统被配置为响应于第一DAC的输出中的寄生光谱性能参数提供调整信号。 寄生光谱性能参数对与第一个DAC相关的定时误差敏感。 校准系统被耦合以向第一DAC提供调整信号以校正第一DAC的定时误差。

公开(公告)号：US08830094B1

公开(公告)日：2014-09-09

申请号：US14132277

申请日：2013-12-18

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann

IPC: H03M1/10 ,  H03M1/36 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0836 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/365

Abstract: An exemplary integrated circuit for performing time skew extraction includes a first subtractor, an array of subtractors separate from the first subtractor, and an array of averaging circuits. Inputs of the first subtractor are coupled to outputs of a plurality of channels of an interleaved analog-to-digital-converter and computes distances between samples of a signal that are measured consecutively by pairs of channels in the plurality of channels. At least some averaging circuits in the array of averaging circuits compute an average of those of the distances that correspond to a respective one of the pairs of channels; one averaging circuit in the array of averaging circuits computes an average of all of the distances. Each subtractor in the array of subtractors computes a difference between an average computed by one of the at least some of the averaging circuits and the average of all of the distances.

Abstract translation: 用于执行时间偏差提取的示例性集成电路包括第一减法器，与第一减法器分离的减法器阵列，以及平均电路阵列。 第一减法器的输入耦合到交错模数转换器的多个通道的输出，并且计算通过多个通道中的通道对连续测量的信号的采样之间的距离。 平均电路阵列中的至少一些平均电路计算对应于该对信道对中的相应距离的那些距离的平均值; 平均电路阵列中的一个平均电路计算所有距离的平均值。 减法器阵列中的每个减法器计算由至少一些平均电路之一计算的平均值与所有距离的平均值之间的差。