公开(公告)号：US20150255499A1

公开(公告)日：2015-09-10

申请号：US14621240

申请日：2015-02-12

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Chien-Hung LIU

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14605 ,  H01L27/14621 ,  H01L27/14685 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A chip package includes a semiconductor chip, insulation layer, redistribution layer and packaging layer and is formed with a cavity. The semiconductor chip has an electronic component and a conductive pad. The conductive pad and the electronic component are disposed on an upper surface of the semiconductor chip and electrically connected. The cavity opens from a lower surface of the semiconductor chip and tapers toward the upper surface to expose the conductive pad. The insulation layer coats the lower surface and a portion of the cavity. The insulation layer is formed with a gap to expose the conductive pad. The redistribution layer coats the lower surface and a portion of the cavity and is electrically connected to the conductive pad through the gap. The packaging layer coats the lower surface and a portion of the cavity.

Abstract translation: 芯片封装包括半导体芯片，绝缘层，再分配层和封装层，并且形成有空腔。 半导体芯片具有电子部件和导电焊盘。 导电焊盘和电子部件设置在半导体芯片的上表面上并电连接。 该空腔从半导体芯片的下表面开口并朝向上表面逐渐变细以暴露导电垫。 绝缘层涂覆下表面和空腔的一部分。 绝缘层形成有间隙以暴露导电垫。 再分布层包覆下表面和空腔的一部分，并通过间隙电连接到导电垫。 包装层涂覆下表面和空腔的一部分。

公开(公告)号：US20150123231A1

公开(公告)日：2015-05-07

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/0236 ,  H01L31/02

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。