中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.019 seconds)

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    1.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
    芯片包装及其制造方法

    公开(公告)号：US20160322305A1

    公开(公告)日：2016-11-03

    申请号：US15139276

    申请日：2016-04-26

    Applicant: XINTEC INC.

    Inventor： Shih-Yi LEE ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Ho-Yin YIU

    IPC: H01L23/538 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/145 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68327 ,  H01L2224/13024 ,  H01L2224/18

    Abstract: A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first though hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the first surface, and the second though hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second though hole to contact the laser stop layer.

    Abstract translation: 芯片封装包括芯片，激光停止层，第一通孔，隔离层，第二通孔和导电层。 激光停止层设置在芯片的第一表面之上，并且第一通孔从芯片的第二表面延伸到第一表面以暴露激光停止层。 隔离层位于第二表面下方，在第一通孔中，隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第一表面，第二通孔穿过第一通孔以暴露激光停止层。 导电层设置在第三表面下方并延伸到第二通孔中以接触激光停止层。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    5.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20170018590A1

    公开(公告)日：2017-01-19

    申请号：US15181291

    申请日：2016-06-13

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

    IPC: H01L27/146

    CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

    Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

    Abstract translation: 提供芯片封装。 芯片封装包括感测装置。 芯片封装还包括设置在感测装置上并电连接到感测装置的第一导电结构。 芯片封装还包括设置在感测装置上的芯片和第二导电结构。 该芯片包括集成电路器件。 第二导电结构位于芯片上并与集成电路器件和第一导电结构电连接。 此外，芯片封装包括覆盖感测装置和芯片的绝缘层。 绝缘层具有孔。 第一导电结构位于孔底部。 绝缘层的顶表面与第二导电结构的顶表面共面。 还提供了一种用于形成芯片封装的方法。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    6.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开
    芯片包装及其形成方法

    公开(公告)号：US20160233260A1

    公开(公告)日：2016-08-11

    申请号：US15013135

    申请日：2016-02-02

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU

    IPC: H01L27/146 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/0216

    CPC classification number: H01L27/14636 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02327 ,  H01L31/1868 ,  H01L2224/11

    Abstract: An embodiment of the invention provides a chip package which includes a first substrate including a device region and having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the second surface of the first substrate and includes a conducting pad structure connected to the device region, and the first substrate completely covers the conducting pad structure. A second substrate is disposed on the second surface of the first substrate and the dielectric layer is located between the first substrate and the second substrate. The second substrate has a first opening exposing a surface of the conducting pad structure, and a redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the exposed conducting pad structure. A method for forming the chip package is also provided.

    Abstract translation: 本发明的一个实施例提供一种芯片封装，其包括包括器件区域并具有第一表面和与其相对的第二表面的第一衬底。 电介质层设置在第一衬底的第二表面上，并且包括连接到器件区域的导电焊盘结构，并且第一衬底完全覆盖导电焊盘结构。 第二基板设置在第一基板的第二表面上，并且电介质层位于第一基板和第二基板之间。 第二基板具有暴露导电焊盘结构的表面的第一开口，并且再分配层保形地设置在第一开口的侧壁和暴露的导电焊盘结构的表面上。 还提供了一种用于形成芯片封装的方法。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    8.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20160204061A1

    公开(公告)日：2016-07-14

    申请号：US14992776

    申请日：2016-01-11

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE

    IPC: H01L23/522 ,  H01L21/304 ,  H01L21/268 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L23/5226 ,  G06K9/0002 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5283 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad. The conductive structure includes a second conductive layer and a laser stopper. The first isolation layer is on the second surface and covering the conductive structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stopper, and the first conductive layer is on the third surface and extended to the second though hole to contact the laser stopper.

    Abstract translation: 一种芯片封装，包括芯片，第一通孔，导电结构，第一隔离层，第二通孔和第一导电层。 第一通孔从第二表面延伸到第一表面以暴露导电焊盘，并且导电结构在第二表面上并延伸到第一通孔以接触导电焊盘。 导电结构包括第二导电层和激光器塞。 第一隔离层位于第二表面上并覆盖导电结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光阻挡件，并且第一导电层在第三表面上并延伸到第二通孔以接触激光器塞。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150206916A1

    公开(公告)日：2015-07-23

    申请号：US14595870

    申请日：2015-01-13

    Applicant: XINTEC INC.

    Inventor： Po-Han LEE ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chien-Hung LIU

    IPC: H01L27/146 ,  H01L31/0203

    CPC classification number: H01L27/14632 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/11

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A redistribution layer, an insulating layer, and a conductive structure are formed on a second surface of the wafer opposite to the first surface, such that a semiconductor element is formed. The semiconductor element is diced from the insulating layer to the carrier, such that the semiconductor element forms at least one sub-semiconductor element. UV light is used to irradiate the sub-semiconductor element, such that adhesion of the temporary bonding layer is eliminated. The carrier of the sub-semiconductor element is removed.

    Abstract translation: 半导体器件的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 在与第一表面相对的晶片的第二表面上形成再分布层，绝缘层和导电结构，从而形成半导体元件。 半导体元件从绝缘层切割到载体，使得半导体元件形成至少一个子半导体元件。 UV光用于照射次半导体元件，从而消除了临时粘合层的粘附。 子半导体元件的载体被去除。

Patent Agency Ranking