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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    31.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 失效
    半导体器件及其制造方法

    公开(公告)号：US20100327318A1

    公开(公告)日：2010-12-30

    申请号：US12735817

    申请日：2009-03-23

    申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

    发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

    IPC分类号： H01L29/205 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66734

    摘要： A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer (2′) is formed on a substrate (1′). A p-type conductive layer (3′) is formed thereon. A second n-type conductive layer (4′) is formed thereon. On the under surface of the substrate (1′), there is a drain electrode (13′) connected to the first n-type conductive layer (2′). On the upper surface of the substrate (1′), there is a source electrode (11′) in ohmic contact with the second n-type conductive layer (4′), and a gate electrode (12′) in contact with the first n-type conductive layer (2′), p-type conductive layer (3′), the second n-type conductive layer (4′) through an insulation film (21′). The gate electrode (12′) and the source electrode (11′) are alternately arranged. The p-type conductive layer (3′) includes In.

    摘要翻译： 提供能够抑制穿通现象发生的半导体器件。 在基板（1'）上形成第一n型导电层（2'）。 在其上形成p型导电层（3'）。 在其上形成第二n型导电层（4'）。 在基板（1'）的下表面上，连接有第一n型导电层（2'）的漏电极（13'）。 在基板（1'）的上表面上存在与第二n型导电层（4'）欧姆接触的源电极（11'）和与第一n型导电层（4'）接触的栅电极（12'） n型导电层（2'），p型导电层（3'），通过绝缘膜（21'）的第二n型导电层（4'）。 栅电极（12'）和源电极（11'）交替排列。 p型导电层（3'）包括In。

    FIELD EFFECT TRANSISTOR
    32.
    发明申请
    FIELD EFFECT TRANSISTOR 有权
    场效应晶体管

    公开(公告)号：US20100224910A1

    公开(公告)日：2010-09-09

    申请号：US12295004

    申请日：2007-03-29

    申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

    发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

    IPC分类号： H01L29/80

    CPC分类号： H01L29/7787 ,  H01L29/2003

    摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x

    摘要翻译： 公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示载流子供应层的Al组成比，t表示p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

    FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR
    34.
    发明申请
    FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR 有权
    场效应晶体管和用于制备场效应晶体管的多层外延膜

    公开(公告)号：US20090045438A1

    公开(公告)日：2009-02-19

    申请号：US12159599

    申请日：2006-10-25

    申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

    发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

    IPC分类号： H01L29/205 ,  H01L29/80

    CPC分类号： H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

    摘要： In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

    摘要翻译： 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并提高载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg / a> = 5，并且在这种情况下， 在不超过5倍（约500）的范围内选择通道层，只要在室温下积聚在通道层中的二维电子气的德布罗意波长即可。

    Schottky Electrode of Nitride Semiconductor Device and Process for Production Thereof
    36.
    发明申请
    Schottky Electrode of Nitride Semiconductor Device and Process for Production Thereof 审中-公开
    氮化硅半导体器件的肖特基电极及其制造方法

    公开(公告)号：US20080006853A1

    公开(公告)日：2008-01-10

    申请号：US11571816

    申请日：2005-07-08

    申请人： Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Okamoto ,  Masaaki Kuzuhara ,  Takashi Inoue ,  Koji Hataya

    发明人： Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Okamoto ,  Masaaki Kuzuhara ,  Takashi Inoue ,  Koji Hataya

    IPC分类号： H01L29/47 ,  H01L21/283 ,  H01L29/812

    CPC分类号： H01L29/475 ,  H01L29/2003 ,  H01L29/812

    摘要： The present invention provides a Schottky electrode for a nitride semiconductor device having a high barrier height, a low leak current performance and a low resistance and being thermally stable, and a process for production thereof. The Schottky electrode for a nitride semiconductor has a layered structure that comprises a copper (Cu) layer being in contact with the nitride semiconductor and a first electrode material layer formed on the copper (Cu) layer as an upper layer. As the first electrode material, a metal material which has a thermal expansion coefficient smaller than the thermal expansion coefficient of copper (Cu) and starts to undergo a solid phase reaction with copper (Cu) at a temperature of 400° C. or higher is employed.

    摘要翻译： 本发明提供了一种用于氮化物半导体器件的肖特基电极，其具有高势垒高度，低漏电流性能和低电阻并且是热稳定的，以及其制造方法。 用于氮化物半导体的肖特基电极具有包括与氮化物半导体接触的铜（Cu）层和形成在作为上层的铜（Cu）层上的第一电极材料层的层状结构。 作为第一电极材料，在400℃以上的温度下开始与铜（Cu）的热膨胀系数小于铜（Cu）的热膨胀系数并开始与铜（Cu）的固相反应的金属材料为 雇用。

    Semiconductor device and field effect transistor
    38.
    发明授权
    Semiconductor device and field effect transistor 有权
    半导体器件和场效应晶体管

    公开(公告)号：US08981434B2

    公开(公告)日：2015-03-17

    申请号：US13393002

    申请日：2010-06-23

    申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

    发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

    IPC分类号： H01L29/76 ,  H01L29/812 ,  H01L29/201 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

    CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

    摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

    摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

    Heterojunction field effect transistor, method for producing heterojunction field effect transistor, and electronic device
    39.
    发明授权
    Heterojunction field effect transistor, method for producing heterojunction field effect transistor, and electronic device 有权
    异质结场效应晶体管，异质结场效应晶体管的制造方法和电子器件

    公开(公告)号：US08674409B2

    公开(公告)日：2014-03-18

    申请号：US13141449

    申请日：2009-12-25

    申请人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

    发明人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7787 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/66462

    摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.

    摘要翻译： 提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。 在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结 如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度 具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

    SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR
    40.
    发明申请
    SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR 有权
    半导体器件和场效应晶体管

    公开(公告)号：US20120199889A1

    公开(公告)日：2012-08-09

    申请号：US13393002

    申请日：2010-06-23

    申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

    发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

    IPC分类号： H01L29/78

    CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

    摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased.A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

    摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。