公开(公告)号：US4648075A

公开(公告)日：1987-03-03

申请号：US669361

申请日：1984-11-08

申请人： Makoto Segawa ,  Shoji Ariizumi

发明人： Makoto Segawa ,  Shoji Ariizumi

IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C29/808

摘要： A redundancy circuit for a semiconductor memory device of the byte configuration type, in which data is read out for each bit, is comprised of a main memory having a plurality of main memory cells arrayed in a matrix fashion, the matrix array being divided into memory sections in the column direction; a spare memory for saving defective memory cells contained in the main memory, the spare memory comprising spare rows of a plurality of spare memory cells arranged in the row direction, the spare row being provided for each of the main memory sections; programmable spare row decoders provided for each row of spare memory cells and for independently selecting each row of the spare memory cell; and main-decoder-disable signal-generating circuits provided for each of the memory sections and for placing all of the row main decoders of the corresponding memory section in non-select state in response to a signal derived from the programmed spare row decoder of the corresponding memory section.

摘要翻译： 用于每个位读出数据的字节配置类型的半导体存储器件的冗余电路由具有以矩阵方式排列的多个主存储单元的主存储器组成，矩阵阵列被分成存储器 列方向的部分; 用于存储包含在主存储器中的有缺陷的存储器单元的备用存储器，所述备用存储器包括沿行方向布置的多个备用存储单元的备用行，为每个主存储器区域提供备用行; 为每行备用存储单元提供可编程备用行解码器，并独立地选择备用存储单元的每一行; 以及为每个存储器部分提供的主解码器禁止信号发生电路，并且用于响应于从编程的备用行解码器导出的信号将相应的存储器部分的所有行主解码器放置在非选择状态 相应的存储器部分。

公开(公告)号：US4453175A

公开(公告)日：1984-06-05

申请号：US187794

申请日：1980-09-16

申请人： Shoji Ariizumi ,  Makoto Segawa

发明人： Shoji Ariizumi ,  Makoto Segawa

IPC分类号： G11C11/412 ,  G11C11/418 ,  H01L21/02 ,  H01L21/764 ,  H01L23/528 ,  H01L27/06 ,  H01L27/11 ,  H01L27/04 ,  G11C11/40 ,  H01L29/78

CPC分类号： H01L28/20 ,  G11C11/412 ,  G11C11/418 ,  H01L21/764 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1112 ,  H01L2924/0002

摘要： A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected, respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

摘要翻译： 一种具有半导体衬底的半导体器件，其中分别与用作第一和第二反相器的负载的第一和第二多晶硅层串联连接的第一和第二绝缘栅FET晶体管晶体管。 第一多晶硅层设置在第二绝缘栅FET晶体管的栅极上方，第二多晶硅层设置在第一绝缘栅FET晶体管的栅电极的上方。

公开(公告)号：US07438665B2

公开(公告)日：2008-10-21

申请号：US11589474

申请日：2006-10-30

申请人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

发明人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

IPC分类号： B60W10/04

CPC分类号： F02D41/0087 ,  B60W2510/1005 ,  B60W2520/10 ,  F01L13/0005 ,  F01L2800/00 ,  F02D41/0225 ,  F02D2200/023 ,  F02D2200/024 ,  F02D2200/0404 ,  F02D2200/0406 ,  F02D2200/0414 ,  F02D2200/703 ,  F16H63/50 ,  Y10T477/675 ,  Y10T477/679 ,  Y10T477/68

摘要： A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

摘要翻译： 一种用于具有多个气缸的内燃机的控制系统和用于在其中操作所有多个气缸的全气缸操作之间进行切换的切换机构和其中多个气缸中的至少一个 气瓶停止。 基于由发动机驱动的车辆的检测到的操作参数来确定用于执行部分缸操作的条件。 当从执行部分气缸操作的状态的车辆操作状态起的预定时间段内检测到的操作参数满足预定的连续状态时，修改确定的结果，使得可以继续部分气缸操作 已经改变为不满足执行部分气缸操作的条件的另一个车辆操作状态。

公开(公告)号：US20070042863A1

公开(公告)日：2007-02-22

申请号：US11589474

申请日：2006-10-30

申请人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

发明人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

IPC分类号： B60W10/04

CPC分类号： F02D41/0087 ,  B60W2510/1005 ,  B60W2520/10 ,  F01L13/0005 ,  F01L2800/00 ,  F02D41/0225 ,  F02D2200/023 ,  F02D2200/024 ,  F02D2200/0404 ,  F02D2200/0406 ,  F02D2200/0414 ,  F02D2200/703 ,  F16H63/50 ,  Y10T477/675 ,  Y10T477/679 ,  Y10T477/68

摘要： A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

摘要翻译： 一种用于具有多个气缸的内燃机的控制系统和用于在其中操作所有多个气缸的全气缸操作之间进行切换的切换机构和其中多个气缸中的至少一个 气瓶停止。 基于由发动机驱动的车辆的检测到的操作参数来确定用于执行部分缸操作的条件。 当从执行部分气缸操作的状态的车辆操作状态起的预定时间段内检测到的操作参数满足预定的连续状态时，修改确定的结果，使得可以继续部分气缸操作 已经改变为不满足执行部分气缸操作的条件的另一个车辆操作状态。

公开(公告)号：US06388938B2

公开(公告)日：2002-05-14

申请号：US09812362

申请日：2001-03-20

申请人： Takao Nakajima ,  Makoto Segawa

发明人： Takao Nakajima ,  Makoto Segawa

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1006 ,  G11C7/1051

摘要： There is provided a semiconductor memory device capable of preventing the deterioration of access characteristics between output signal lines. The semiconductor memory device comprises: first and second cell arrays, each of which has the same number of memory cells; first through (2n−1)-th (n≧1) output selection control circuits; first through (2n−1)-th output transistor circuits which are provided so as to correspond to the first through (2n−1)-th output selection control circuits, and each of which receives the output of a corresponding one of the output transistor circuits; and first through (4n−2)-th output signal lines, each of the first and second cell arrays being divided into k (k≧2) first through k-th section parts, each of which has 2n−1 first through (2n−1)-th output parts and at least one auxiliary input/output part, the i-th (i=1, . . . , n−1) output selection control part receiving the output of the (2i−1)-th input/output part of each of the first through k-th section parts of the first cell array via the (2i−1)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the first cell array via the 2i-th output signal line, the n-th output selection control part receiving the output of the (2n−1)-th input/output part of each of the first through k-th section parts of the first cell array via the (2n−1)-th output signal line and receiving the output of the auxiliary input/output part of each of the section parts of the first cell array via the 2n-th output signal line, and the (n+i)-th (i=1, . . . , n−1) output control circuit receiving the output of the (2i−1)-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i−1)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i)-th output signal line.

公开(公告)号：US6037638A

公开(公告)日：2000-03-14

申请号：US34316

申请日：1998-03-04

申请人： Mitsuhiro Abe ,  Yoichi Suzuki ,  Makoto Segawa

发明人： Mitsuhiro Abe ,  Yoichi Suzuki ,  Makoto Segawa

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： The gates 31, 32, 33 and 34 of a pair of driver transistors Q1, Q2 and a pair of address-selecting transistors Q3, Q4 are arranged so as to be perpendicular to bit lines BL, /BL. The drain regions of the driver transistors Q1, Q2 forming a flip-flop are arranged point-symmetrically around an element isolating region. The source regions of the driver transistors Q1, Q2 are arranged point-symmetrically. Similarly, the address-selecting transistors Q3, Q4 are arranged point-symmetrically. An upper wiring layer connected to two gates of the transistors are arranged so as to be perpendicular to the bit lines BL, /BL. Two Vss lines are formed in the same layer as that for the bit lines BL, /BL and arranged on both sides of the bit lines BL, /BL in parallel thereto. The Vss lines are connected to the source regions of the driver transistors. With this construction, the bi-stability of a memory cell used for a semiconductor memory device, such as a SRAM, is improved, so that the low-voltage operation and the hold characteristic are improved and software errors are removed. In addition, the aspect ratio of the cell is changed from the aspect ratio of a conventional, longitudinally extending cell to the aspect ratio of a laterally extending cell, so that the lengths of the bit lines are decreased to achieve a high speed operation.

摘要翻译： 一对驱动晶体管Q1，Q2和一对地址选择晶体管Q3，Q4的栅极31,32,33和34被布置成垂直于位线BL / BL。 形成触发器的驱动晶体管Q1，Q2的漏极区域围绕元件隔离区域对称布置。 驱动晶体管Q1，Q2的源极区域对称布置。 类似地，地址选择晶体管Q3，Q4被点对称地排列。 连接到晶体管的两个栅极的上部布线层被布置成垂直于位线BL / BL。 两条Vss线形成在与位线BL，/ BL相同的层中，并且平行布置在位线BL，/ BL两侧。 Vss线连接到驱动晶体管的源极区域。 利用这种结构，用于诸如SRAM的半导体存储器件的存储单元的双稳态性得到改善，从而提高了低电压操作和保持特性，并且消除了软件错误。 此外，单元的纵横比从常规的纵向延伸单元的纵横比变化到横向延伸单元的纵横比，从而减小位线的长度以实现高速操作。

公开(公告)号：US5440512A

公开(公告)日：1995-08-08

申请号：US44115

申请日：1993-04-08

申请人： Takayuki Harima ,  Makoto Segawa

发明人： Takayuki Harima ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C7/10 ,  G11C11/409 ,  G11C11/413 ,  G11C11/417

CPC分类号： G11C7/1051 ,  G11C7/1057

摘要： A semiconductor memory device includes an address input circuit for receiving an address signal and outputting an internal address signal corresponding to the received address signal; an address decoder for decoding the internal address signal and outputting a decoded signal; a memory cell array having a plurality of memory cells each capable of storing data, as selected by the decoded signal, the selected memory cell outputting memory cell data; and an output circuit for outputting a truth data and false data at the same time in accordance with the output memory cell data of the selected memory cell.

摘要翻译： 半导体存储器件包括地址输入电路，用于接收地址信号并输出​​对应于接收到的地址信号的内部地址信号; 地址解码器，用于解码内部地址信号并输出​​解码信号; 具有多个存储单元的存储单元阵列，每个存储单元都能够存储由所述解码信号选择的输出存储单元数据的所选存储单元的数据; 以及输出电路，用于根据所选存储单元的输出存储单元数据同时输出真值数据和伪数据。

公开(公告)号：US5136542A

公开(公告)日：1992-08-04

申请号：US599637

申请日：1990-10-18

申请人： Sumako Abe ,  Makoto Segawa

发明人： Sumako Abe ,  Makoto Segawa

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/10 ,  G11C11/417 ,  H03K19/0175

CPC分类号： G11C7/1051 ,  G11C5/14

摘要： A semiconductor memory device having an internal circuit which is powered from a first power source terminal and outputs an output drive signal corresponding to a stored data in a selected memory cell of a memory cell array; and output buffer unit which is powered from a second power source terminal and operates in such a manner that a gate is closed or opened in accordance with whether the output drive signal is low level or high level, and an output signal of low level or high level corresponding to closed gate or opened gate is outputted via an external output terminal to the external; and a level change suppressing circuit for suppressing a level change of the output drive signal as viewed from the output buffer, by connecting the output terminal of the internal circuit to one of the second power source terminal and the external output terminal, when the potential at the second power source terminal changes relatively with respect to the potential at the first power source terminal as the output signal at the external output terminal changes its level between low level and high level.

摘要翻译： 一种半导体存储器件，其具有由第一电源端子供电的内部电路，并将对应于存储的数据的输出驱动信号输出到存储单元阵列的所选择的存储单元中; 以及输出缓冲器单元，其由第二电源端子供电，并且以根据输出驱动信号是低电平还是高电平关闭或打开门的方式操作，以及低电平或高电平的输出信号 对应于闭门或开门的电平经由外部输出端输出到外部; 以及电平变化抑制电路，用于通过将内部电路的输出端子连接到第二电源端子和外部输出端子之一来抑制从输出缓冲器观察的输出驱动信号的电平变化，当电位 当外部输出端子的输出信号在低电平和高电平之间变化时，第二电源端子相对于第一电源端子的电位相对变化。

公开(公告)号：US5043944A

公开(公告)日：1991-08-27

申请号：US611056

申请日：1990-11-09

申请人： Kenichi Nakamura ,  Makoto Segawa

发明人： Kenichi Nakamura ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417

CPC分类号： G11C7/1057 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells, each of the cells being capable of storing a data and being selected by an address; a pair of data lines to which a pair of complementary data from a selected memory cell are imputted; an equalizer for short-circuiting and equalizing the pair of data lines when an equalizing signal is applied; an output circuit for outputting a single signal corresponding to the pair of complementary data from the pair of data lines; a pair of latch circuits provided between the output circuit and the equalizer for the pair of data lines, the pair of latch circuits holding the pair of complementary data; a pair of output buffer circuit provided between the pair of latch circuits and the equalizer for the pair of data lines, the pair of output buffer circuits capable of taking a low impedance state wherein the potentials per se of the pair of data lines are outputted, and a high impedance state wherein the potential change of the pair of data lines is not transmitted to the output side of the pair of output buffer circuits; and a controller for generating a first control signal which makes the pair of output buffer circuits to enter the high impedance state before the equalizing signal is applied to the equalizer and a second control signal which makes the pair of output buffer circuits to enter the low impedance state after the equalizing signal is turned off.

公开(公告)号：US4725746A

公开(公告)日：1988-02-16

申请号：US421885

申请日：1982-09-23

申请人： Makoto Segawa ,  Shoji Ariizumi

发明人： Makoto Segawa ,  Shoji Ariizumi

IPC分类号： H03K19/017 ,  H03K4/24 ,  H03K ,  H03K17/06 ,  H03K17/687

CPC分类号： H03K19/01714

摘要： A semiconductor circuit has first and second MOS transistors which are connected between an output terminal and a positive and a reference power source terminal, respectively, a bootstrap capacitor connected between the output terminal and the gate of the first MOS transistor, an inverter which inverts the input signal and which supplies the inverted signal to the gate of the second MOS transistor after a predetermined delay timne, and a switching MOS transistor having a current path connected between the input terminal and the gate of the first MOS transistor. The switching MOS transistor has a threshold voltage greater than that of the second MOS transistor.

摘要翻译： 半导体电路具有分别连接在输出端和正极和基准电源端之间的第一和第二MOS晶体管，连接在第一MOS晶体管的输出端和栅极之间的自举电容器，反相器 并且在经过预定延迟时间之后将反相信号提供给第二MOS晶体管的栅极;以及开关MOS晶体管，其具有连接在第一MOS晶体管的输入端和栅极之间的电流通路。 开关MOS晶体管的阈值电压大于第二MOS晶体管的阈值电压。